參數(shù)資料
型號: SY89853UMG
廠商: Micrel Inc
文件頁數(shù): 3/9頁
文件大小: 0K
描述: IC CLOCK MUX 2:1 2.5GHZ 32-MLF
標準包裝: 60
系列: Precision Edge®
類型: 多路復用器
電路數(shù): 2
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,PECL
輸出: LVPECL
頻率 - 最大: 2.5GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應商設備封裝: 32-MLF?(5x5)
包裝: 管件
其它名稱: 576-3710
SY89853UMG-ND
Micrel, Inc.
SY89853U
August 2007
3
M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead Finish
SY89853UMG
QFN-32
Industrial
SY89853U with Pb-Free bar-line indicator
NiPdAu Pb-Free
SY89853UMGTR
(2)
QFN-32
Industrial
SY89853U with Pb-Free bar-line indicator
NiPdAu Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
32-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
25, 28,
29, 32
1, 4
5, 8
INA0, /INA0,
INA1, /INA1,
INB0, /INB0,
INB1, /INB1
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50
. Note that these inputs will default to an indeterminate
state if left open. Connecting one input to VCC and the complementary input-to-GND
through 1k
resistor can terminate unused differential input pairs. The VT pin is to be left
open in this configuration. Please refer to the “Input Interface Applications” section for more
details.
10, 13, 16, 17,
20, 23
VCC
Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors. The 0.01F
capacitor should be as close to VCC pin as possible.
14, 19
NC
Not connected.
18
15
SELA,
SELB
Bank A and Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible
inputs select the inputs to the multiplexers. These inputs are internally connected to a
25k
pull-up resistor and will default to logic HIGH state if left open.
22, 21
12, 11
QA, /QA,
QB, /QB
Differential Outputs: These LVPECL output pairs are the outputs of the device. They are a
logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to
the “Truth Table” below for details.
26, 30
2, 6
VTA0, VTA1
VTB0, VTB1
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT
pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for details.
27
31
3
7
VREF-ACA0,
VREF-ACA1,
VREF-ACB0,
VREF-ACB1
Reference Voltages: These reference voltage outputs are equivalent to VCC-1.2V. They are
used for AC-coupled inputs. Connect VREF-AC directly to the VT pin and bypass with
0.01
F low ESR capacitor to VCC. See Input Interface Applicationssection. Maximum
sink/source current is
±1.5mA.
9, 24
GND,
Exposed Pad
Ground: Ground pins and exposed pad must be connected to the same ground plane.
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