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參數(shù)資料
| 型號(hào)： | SY898531LTZ TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:9 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 500MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
7
SY88843V
Micrel, Inc.
M9999-110905
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88843V low-power, limiting post amplifier operates
from a single +3.3V
±10% or +5V ±10% power supply, over
an industrial temperature range of –40
°C to +85°C. Signals
with data rates up to 3.2Gbps and as small as 10mVPP can
be amplified. Figure 1 shows the allowed input voltage swing.
The SY88843V generates an SD output, providing feedback
to EN for output stability. SDLVL sets the sensitivity of the
input amplitude detection.
Input Amplifier/Buffer
The SY88843V’s inputs are internally terminated with 50
to REF. Unless unaffected by this internal termination
scheme, upstream devices need to be AC-coupled to the
SY88843V’s inputs. Figure 2 shows a simplified schematic
of the input structure.
The high sensitivity of the input amplifier detects and
amplifies as small as 10mVPP. The input amplifier allows
input signals as large as 1800mVPP. Input signals are linearly
amplified with a typically 38dB differential voltage gain. Since
it is a limiting amplifier, the SY88843V outputs typically
800mVPP voltage-limited waveforms for input signals that
are greater than 10mVPP. Applications requiring the
SY88843V to operate with high gain should have the
upstream TIA placed as close as possible to the SY88843V’s
input pins to ensure the device's best performance of the
device.
Output Buffer
The SY88843V’s CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to VCC or
equivalent for each output pin provides buffer termination.
Figure 3 shows a simplified schematic of the output structure
and includes an appropriate termination method. Of course,
driving a downstream device with a CML input that is
internally terminated with 50
to VCC eliminates the need
for external termination. As noted in the previous section,
the amplifier outputs, typically 800mVPP, waveforms across
25
total loads. The output buffer, thus, switches typically
16mA tail-current. Figure 4 shows the power supply current
measurement which excludes the 16mA tail-current.
Signal Detect
The SY88843V incorporates a chatter-free, SD open-
collector TTL output with internal 4.75k
pull-up resistor as
shown in Figure 5. SD is used to determine that the input
amplitude large enough to be considered a valid input. SD
asserts high if the input amplitude rises above the threshold
set by SDLVL and de-asserts low otherwise. SD can be fed
back to the enable (EN) input to maintain output stability
under a loss-of-signal condition. EN de-asserts low the true
output signal without removing the input signals. Typically,
4.6dB SD hysteresis is provided to prevent chattering.
Signal Detect-Level Set
A programmable, signal-detect level set pin sets the
threshold of the input amplitude detection. Connecting an
external resistor between VCC and SDLVL sets the voltage
at SDLVL. This voltage ranges from V
CC to VREF. The
external resistor creates a voltage divider between V
CC and
REF as shown in Figure 6. If desired, an appropriate external
voltage may be applied rather than using a resistor. The
relationship between V
SDLVL and RSDLVL is given by:
VV
–
R
R+
SDLVL
CC
SDLVL
=
13
28
.
where voltages are in volts and resistances are in k
.
The smaller the external resistor, which implies a smaller
voltage difference from SDLVL to VCC, the lower the SD
sensitivity. Hence, larger input amplitude is required to assert
SD. The “Typical Operating Characteristics” section contains
graphs showing the relationship between the input amplitude
detection sensitivity and VSDLVL or RSDLVL.
Hysteresis
The SY88843V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
the ratios change linearly. Therefore, the optical hysteresis
in dB is half the electrical hysteresis in dB given in the
datasheet. The SY88843V provides typically 2.3dB SD
optical hysteresis. As the SY88843V is an electrical device,
this datasheet refers to hysteresis in electrical terms. With
4.6dB SD hysteresis, a voltage factor of 1.7 is required to
assert SD.
Hysteresis and Sensitivity Improvement
If increased SD sensitivity and hysteresis are required,
an application note entitled “Notes on Sensitivity and
Hysteresis in Micrel Post Amplifiers” is available at http://
www.micrel.com/product-info/app_hints+notes.shtml.
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