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參數(shù)資料
| 型號(hào)： | SY898531LTZ TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:9 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類(lèi)型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 500MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
Micrel, Inc.
SY898531L
June 25, 2013
3
Revision 2.0
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
7
VEE
Ground.
8
CLK_EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0
Q8 outputs. It is
internally connected to a 50k
pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. Since CLK_EN is synchronous
with the input clock, the outputs will be enabled/disabled following a rising and a falling
edge of the input clock. VTH = is approximately 1.5V.
4
CLK_SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the input to the
multiplexer. Note that this input is internally connected to a 50k pull-down resistor and will
default to logic LOW state if left open. VTH = is approximately 1.5V.
2, 3
CLK, /CLK
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. CLK is internally connected to a 28k
pull-down
resistor and will default to a logic LOW state if left open while /CLK is connected to a 50k
pull-up resistor and will default to a logic HIGH state if left open. This input pair is selected
when CLK_SEL is set to logic LOW.
5, 6
PCLK, /PCLK
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. PCLK is internally connected to a 50k
pull-down
resistor and will default to a logic LOW state if left open while /PCLK is connected to a
50k
pull-up resistor and will default to a logic HIGH state if left open. This input pair is
selected when CLK_SEL is set to logic HIGH.
1
VCC
Positive Power Supply Pin: Bypass with 0.1F||0.01F low-ESR capacitor as close to the
VCC pin as possible.
9, 16, 17, 24, 25, 32
VCCO
Output Positive Power Supply Pins: Bypass with 0.1F||0.01F low-ESR capacitors as
close to the VCCO pins as possible.
30, 31
28, 29
26, 27
22, 23
20, 21
18, 19
14, 15
12, 13
10, 11
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
LVPECL Differential Output Pairs: Differential buffered output copies of the selected input
signal. The output swing is typically 800mV. Unused output pairs may be left floating with
no impact on jitter. These differential LVPECL outputs are a logic function of the CLK, /CLK
and PCLK, /PCLK, and CLK_SEL inputs (see Truth Table).
Truth Table
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0 :Q8
/Q0:/Q8
0
CLK, /CLK
Disabled : LOW
Disabled : HIGH
0
1
PCLK, /PCLK
Disabled : LOW
Disabled : HIGH
1
0
CLK, /CLK
CLK
/CLK
1
PCLK, /PCLK
PCLK
/PCLK
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| SY898533L | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:Precision Differential 3.3V Low Skew LVPECL 1:4 Fanout Buffer |
| SY898533LKZ | 功能描述:緩沖器和線路驅(qū)動(dòng)器 3.3V LVPECL 1:4 Fanout Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY898533LKZ TR | 功能描述:緩沖器和線路驅(qū)動(dòng)器 3.3V LVPECL 1:4 Fanout Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY898533LKZTR | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:Precision Differential 3.3V Low Skew LVPECL 1:4 Fanout Buffer |
| SY898535L | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:Precision Differential 3.3V, Low Skew, 1:4 LVCMOS/LVTTL -to-LVPECL Fanout Buffer |
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