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參數(shù)資料
| 型號： | SY89841UMG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX 2:1 LVDS RPE 16-MLF |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | SY89 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 2:1 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2095-5 SY89841UMG-ND |
Micrel, Inc.
SY89841U
February 2005
M9999-021405
hbwhelp@micrel.com or (408) 955-1690
10
Case #4: Input Clock Failure: Switching from the
selected clock input stuck in an undetermined state
to a valid clock input (RPE enabled).
If CLK1 fails to an undetermined state (e.g.,
amplitude falls below the 100mV (VIN) minimum
single-ended input limit, or 200mV differentially)
before the RPE MUX selects CLK2 (using the SEL
pin), the switchover to the valid clock CLK2 will
occur either following Case #2 or Case #3,
depending upon the last valid state at the CLK1
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a
slowly deteriorating (but still toggling) input signal.
Due to the FSI function, the propagation delay will
depend on rise and fall time of the input signal and
on its amplitude. Refer to “Typical Operating
Characteristics” for detailed information.
CLK1
CLK2
SEL
OUTPUT
Select CLK1
Select CLK2
as in case #2
as in case #3
Timing Diagram 4
Power-On Reset (POR) Description
The SY89841U includes an internal power-on reset
(POR) function to ensure the RPE logic starts-up in
a known logic state once the power-supply voltage is
stable. An external capacitor connected between VCC
and the CAP pin (pin 11) controls the delay for the
power-on reset function.
The required capacitor value calculation is based
upon the time the system power supply needs to
power up to a minimum of 2.3V. The time constant
for the internal power-on-reset must be greater than
the time required for the power supply to ramp up to
a minimum of 2.3V.
The following formula describes this relationship:
C( F)
t
(ms)
12(ms/ F)
dPS
≥
As an example, if the time required for the system
power supply to power up past 2.3V is 12ms, then
the required capacitor value on pin 11 would be:
C( F)
12ms
12(ms/ F)
≥
C1 F
≥
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89841UMG TR | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Precision 2:1 LVDS MUX w/ RPE & FSI (I Temp, Green) RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SY89841UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVDS Runt Pulse Eliminator 2:1 Multiplexer |
| SY89842U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision CML Runt Pulse Eliminator 2:1 |
| SY89842U_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision CML Runt Pulse Eliminator 2:1 |
| SY89842UMG | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Precision 2:1 CML MUX w/ RPE & FSI (I Temp, Green) RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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