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參數(shù)資料
型號(hào): SY89834UMI
廠商: Micrel Inc
文件頁數(shù): 9/10頁
文件大?。?/td> 0K
描述: IC CLK BUF MUX TRNSLA 2:4 16-MLF
標(biāo)準(zhǔn)包裝: 100
系列: Precision Edge®
類型: 扇出緩沖器(分配),多路復(fù)用器,變換器
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無/是
輸入: LVCMOS,LVTTL
輸出: LVPECL
頻率 - 最大: 1GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 管件
Micrel, Inc.
SY88149HAL
July 2011
8
M9999-072511-A
hbwhelp@micrel.com or (408) 955-1690
Detailed Description
The SY88149HAL is a high-sensitivity limiting post
amplifier which operates on a +3.3V power supply over
the industrial temperature range. Signals with data rates
up to 1.25Gbps and as small as 5mVpp can be amplified.
Depending on the LOS/SD SEL option, the SY88149HAL
can generate an SD or LOS output, and allow feedback to
the JAM input for output stability. LOS/SDLVL sets the
sensitivity of the input amplitude detection.
To satisfy the stringent timing requirements of the
GPON specifications, the signal detect circuit offers 5ns
SD assert (LOS deassert) time and the option to
deassert SD (assert LOS) using the /AUTO RESET or
manual RESET function. When /AUTO RESET is
enabled, SD deasserts/LOS asserts automatically within
120ns after the last high-to-low transition of the input
burst. When the /AUTORESET function is disabled, the
SD deassert/LOS assert time can be reset by using the
provided RESET pin.
Input Buffer
Figure 2 shows a simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals as
small as 5mVpp to be detected and amplified. The input
buffer can allow input signals as large as 1800mVPP. Input
signals are linearly amplified with a typically 48dB
differential voltage gain until the outputs reach 1500mVPP
(typical). Applications requiring the SY88149HAL to
operate with high-gain should have the upstream TIA
placed as close as possible to the SY88149HAL’s input
pins. This ensures the best performance of the device.
Output Buffer
The SY88149HAL’s LVPECL output buffer is designed
to drive 50 lines. The output buffer requires
appropriate termination for proper operation. An external
50 resistor to VCC – 2V for each output pin provides
this. Figure 3 shows a simplified schematic of the output
stage.
Loss of Signal/Signal Detect
The SY88149HAL generates a chatter-free Signal-Detect
(SD) or LOS LVTTL output, as shown in Figure 4. A
highly-sensitive signal detect circuit is used to determine
that the input amplitude is too small to be considered a
valid input. LOS asserts high if the input amplitude falls
below the threshold sets by LOS/SDLVL and deasserts
low otherwise. SD asserts high if the input amplitude rises
above threshold set by LOS/SDLVL and deasserts low
otherwise. LOS/SD can be fed back to the JAM input to
maintain output stability under the absence of an invalid
signal condition. Typically, a 3dB hysteresis is provided to
prevent chattering.
LOS/SD Level Set
A programmable LOS/SD level pin (LOS/SDLVL) sets the
threshold of the input amplitude detection. Connecting an
external resistor between VCC and LOS/SDLVL sets the
voltage at LOS/SDLVL. This voltage ranges from VCC to
VREF. The external resistor creates a voltage divider
between VCC and VREF, as shown in Figure 5. Set the
LOS/SDLVL voltage closer to VREF or more sensitive
LOS/SD detection or closer to VCC for higher inputs.
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