Precision Edge SY89834U Micrel, Inc. M9999-080505 hbwhelp@micrel.com or (408) 955-1690 IN1 IN2 EN SEL" />
參數(shù)資料
型號(hào): SY89834UMI
廠商: Micrel Inc
文件頁數(shù): 3/10頁
文件大?。?/td> 0K
描述: IC CLK BUF MUX TRNSLA 2:4 16-MLF
標(biāo)準(zhǔn)包裝: 100
系列: Precision Edge®
類型: 扇出緩沖器(分配),多路復(fù)用器,變換器
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無/是
輸入: LVCMOS,LVTTL
輸出: LVPECL
頻率 - 最大: 1GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 管件
2
Precision Edge
SY89834U
Micrel, Inc.
M9999-080505
hbwhelp@micrel.com or (408) 955-1690
IN1
IN2
EN
SEL
Q0–Q3
/Q0–Q3
0
X
110
1
X
111
0
X
0100
1
X
1101
0
XX
0
X
0(1)
Note:
1. On next negative transition of the input signal (IN).
TRUTH TABLE
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89834UMI
MLF-16
Industrial
834U
Sn-Pb
SY89834UMITR(2)
MLF-16
Industrial
834U
Sn-Pb
SY89834UMG(3)
MLF-16
Industrial
834U with Pb-Free
NiPdAu
bar line indicator
Pb-Free
SY89834UMGTR(2, 3)
MLF-16
Industrial
834U with Pb-Free
NiPdAu
bar line indicator
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Pin Number
Pin Name
Pin Function
15, 16
Q0, /Q0
Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies
1, 2,
Q1, /Q1
of the inputs. Please refer to the “Truth Table” section for details. Unused output pairs may be
3, 4,
Q2, /Q2
left open. Terminate wtih 50
to V
CC–2V. See “Output Termination Recommendations” section
5, 6
Q3, /Q3
for more details.
8
EN
This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable will only occur when the outputs are in a logic
LOW state. Note that this input is internally connected to a 25k
pull-up resistor and will default
to logic HIGH state (enabled) if left open.
12,
IN1
Single-ended TTL/CMOS-compatible inputs to the device. These inputs are internally connected
9
IN2
to a 25k
pull-up resistor and will default to logic HIGH state if left open. The input threshold is
VCC/2.
10
NC
No connect. Not internally connected.
11
SEL
TTL/CMOS Compatible Select Input for signals IN1 and IN2. The input threshold is V
CC/2. HIGH at
the SEL input selects signal IN1. LOW at the SEL input selects signal IN2. SEL includes a 25k
pull-up resistor. The default state is HIGH when left floating.
13
GND
Ground. GND pins and exposed pad must be connected to the most negative potential of the
device ground.
7, 14
VCC
Positive Power Supply: Bypass with 0.1
F//0.01F low ESR capacitors and place as close to
each VCC pin as possible.
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
Q1
/Q1
Q2
/Q2
IN1
SEL
NC
IN2
/Q0
Q0
VCC
GND
Q3
/Q3
VCC
EN
16-Pin MLF (MLF-16)
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