參數(shù)資料
型號: SY89809ALTZTR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: LEAD FREE, TQFP-32
文件頁數(shù): 1/8頁
文件大?。?/td> 285K
代理商: SY89809ALTZTR
SY89809AL
3.3V LVPECL/HSTL to HSTL 1:9 High-
Performance Clock Driver with LVTTL
Clock Select and Enable
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
July 2010
M9999-070110
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89809AL is a high-performance bus clock driver
with nine differential High-Speed Transceiver Logic (HSTL)
output pairs. The part is designed for use in low-voltage
(3.3V/1.8V) applications, which require a large number of
outputs to drive precisely aligned, ultra-low skew signals to
their destination. The input is multiplexed from either HSTL
or Low-Voltage Positive-Emitter-Coupled Logic (LVPECL)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous
so
that
the
outputs
will
only
be
enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse
when the device is enabled/disabled as can happen with
an asynchronous control.
The SY89809AL features low pin-to-pin skew (15ps
typical) and low part-to-part skew (100ps typical). The
SY89809AL is available in a single space-saving package,
enabling a lower overall cost solution.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Block Diagram
Precision Edge
Features
3.3V core supply, 1.8V output supply for reduced power
LVPECL and HSTL inputs
Nine differential HSTL (low-voltage swing) output pairs
HSTL outputs drive 50-to-ground with no offset voltage
750MHz maximum clock frequency
Low part-to-part skew (100ps typical)
Low pin-to-pin skew (15ps typical)
Available in 32-pin TQFP
Applications
High-performance PCs
Workstations
Parallel processor-based systems
Other high-performance computing
Communications
Level
Direction
Signal
HSTL
Input
HSTL_CLK, /HSTL_CLK
HSTL
Output
Q0 – Q8, /Q0 – /Q8
LVPECL
Input
LVPECL_CLK, /LVPECL_CLK
LVCMOS/LVTTL
Input
CLK_SEL, OE
Table 1. Signal Groups
OE
(1)
CLK_SEL
Q0 – Q8
/Q0 – /Q8
0
LOW
HIGH
0
1
LOW
HIGH
1
0
HSTL_CLK
/HSTL_CLK
1
LVPECL_CLK
/LVPECL_CLK
Table 2. Truth Table
Note:
1. The OE (output enable) signal is synchronized with the low level of
the HSTL_CLK and LVPECL_CLK signal.
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參數(shù)描述
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