參數資料
| 型號： | SY89538LHZ TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 18/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZR LVPECL/LVDS 64TQFP |
| 標準包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 時鐘合成器/扇出緩沖器 |
| PLL： | 是 |
| 輸入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 756MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應商設備封裝： | 64-EP-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY89538LHZTR SY89538LHZTR-ND |
Micrel, Inc.
SY89538L
January 2008
M9999-010808-E
hbwhelp@micrel.com or (408) 955-1690
4
Pin Description
Power
Pin Number
Pin Name
Pin Function
1
VCCA
Analog PLL Power Pin. Connects to “quiet” 3.3V supply. 3.3V power pins must be
connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitors and
place them as close to the VCCA pin as possible.
6, 56
VCCD
Digital Logic Core Power Pin. VCCD connects to a 3.3V supply. All power pins must
be connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitors
and place them as close to the VCCD pin as possible.
19, 40, 43, 51
VCCO
LVDS and LVPECL Output Driver Power Pins. These outputs can be powered from a
2.5V or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V ±10% or
2.5V ±5%. All power pins must be connected together on the PCB. Bypass with
0.1F//0.01F low ESR capacitor and place them as close to the VCCO pin as
possible.
15
GNDA
Analog PLL Ground. Connect to “quiet” ground. GNDA and GND must be connected
together on the PCB.
16, 30, 31,
47, 55
GND,
Exposed Pad
Ground: GND pins and exposed pad must both be connected to the same ground
plane.
Control and Configuration
Pin Number
Pin Name
Pin Function
62
LR
Analog Input/Output. Provides the reference voltage for the PLL loop filter and is
used with the LF pin. See “External Loop Filter Considerations” for recommended
loop filter values.
63
LF
Analog Input/Output. Provides the loop filter node for the PLL. See “External Loop
Filter Considerations” for recommended loop filter values.
2, 7
RSEL1, RSEL0
TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inputs.
The two-bit input pre-scalar divides the input reference frequency by /1, /2, /4, or /8.
RSEL0 is the LSB bit. See “Reference Input Divider and Zero Delay MUX Divider
Select Table” for proper decoding. The threshold voltage VTH = VCC/2. Internal 25k
pull-up. The default logic is HIGH.
10
INSEL
TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input.
Internal 25k pull-up. The default is logic HIGH, and selects the XTAL input. The
threshold voltage VTH = VCC/2.
Logic HIGH: XTAL Select
Logic LOW: Reference Input Select
36
LSEL
TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL,
DSEL, and LEN are used together to decode the selection and post divider of the
LVDS outputs. Internal 25k pull-up. See “LVDS Output Post-Divider and Frequency
Select Table” for proper decoding. The threshold voltage VTH = VCC/2. The default
logic is HIGH.
37
LEN
TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and acts as
a frequency select pin. LEN, DSEL, and LSEL are used together to decode the
selection and post divide of the LVDS output bank, see the “LVDS Output Post-
Divider and Frequency Select Table” for proper decoding. Internal 25k pull-up.
When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are
HIGH. The threshold voltage VTH = VCC/2. The default logic is HIGH.
23
25
57
59
PSEL0
PSEL1
PSEL2
PSEL3
TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx,
DSEL and PENx are used together to decode the selection and post divider of the
PECL outputs. PSELx pins include an internal 25k pull-up. The threshold voltage
VTH = VCC/2. See "LVPECL Output Post-Divider and Frequency Select Table” for
proper decoding.
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