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參數(shù)資料
| 型號： | SY89538L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
| 中文描述： | 3.3精密LVPECL和LVDS可編程多個OUTPUT銀行時鐘合成器與扇出緩沖器與零延遲 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大小： | 628K |
| 代理商： | SY89538L |
Micrel, Inc.
Pin Description
Control and Configuration
(continued)
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
5
Pin Number
Pin Name
Pin Function
24
26
58
60
PEN0
PEN1
PEN2
PEN3
TTL/CMOS input enable pin. Used to control the PECL POUT0-POUT3 outputs and
as a frequency select pins. PENx, PSELx, and DSEL are used together; see the
“LVPECL Output Post-Divider and Frequency Select Table” for proper decoding.
PENx contains internal 25k
pull-up. When disabled, PECL0-PECL3 outputs are a
logic LOW. The threshold voltage V
TH
= V
CC
/2.
TTL/CMOS Output Bank Synchronization Control. Internal 25k
pull-down. The
default state is HIGH. After any bank has been programmed, all PECL and LVDS
outputs are synchronized when the SYNC control pin is toggled with a HIGH-LOW-
HIGH transition. See “Synchronization” section for details. The threshold voltage V
TH
= V
CC
/2.
TTL/CMOS Input Select Control. Selects either internal or external feedback (zero-delay
function). Internal 25k
pull-up. The threshold voltage V
TH
= V
CC
/2. Default is logic
HIGH, and selects internal feedback.
Logic HIGH: Internal feedback (from the Programmable Divider)
Logic Low: External feedback (from the FBIN inputs)
46
SYNC
5
FBSEL
28
33
35
PD_4
PD_2
PD_0
TTL/CMOS Programmable Divider-Select Control. Internal 25k
pull-down. Default is
logic LOW. The threshold voltage V
TH
= V
CC
/2. See “Programmable-Divider Select Table”
for proper decoding.
27
29
34
PD_5
PD_3
PD_1
TTL/CMOS Programmable Divider-Select Control. Internal 25k
pull-up. Default is logic
HIGH. The threshold voltage V
TH
= V
CC
/2. See “Programmable-Divider Select Table” for
proper decoding.
13, 14
PDSEL1,
PDSEL0
TTL/CMOS Pre-Divider Select Input. Internal 25k
pull-up. This two-bit input divider
scales the VCO/2 frequency. See “Pre-Divider Frequency Select Table” for proper
decoding. The threshold voltage V
TH
= V
CC
/2.
TTL/CMOS Post-Divider Option Control. Internal 25k
pull-up. Default is logic HIGH.
The threshold voltage V
TH
= V
CC
/2.
Logic HIGH: All LVPECL and LVDS outputs operate with their respective output
frequency control (PSELx, PENx, LSEL, LEN).
Logic LOW: Internal PLL is disabled, reference and XTAL signals by-passes the PLL
through a /1, /4, and /16 Post-Divider.
See “LVPECL and LVDS Output Post-Divider and Frequency Select Table” for proper
decoding.
22
DSEL
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| SY89538LHG | 功能描述:IC SYNTH/BUFF LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHG TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
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