參數(shù)資料
型號(hào)： SY89538L
廠商： Micrel Semiconductor,Inc.
英文描述： 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY
中文描述： 3.3精密LVPECL和LVDS可編程多個(gè)OUTPUT銀行時(shí)鐘合成器與扇出緩沖器與零延遲
文件頁(yè)數(shù)： 12/23頁(yè)
文件大?。?/td> 628K
代理商： SY89538L
Micrel, Inc.
Functional Description
Overall Function
The SY89538L integrated programmable clock
synthesizer and fanout buffer with zero delay is part of
a precision PLL-based clock generation family
optimized for internal system clock generation
(FPGAs, ASICs, NPU).
Inputs
XTAL
The SY89538L features a fully integrated on-board
oscillator, which minimizes system implementation
cost. The oscillator is a series resonant, multi-vibrator
type crystal driver designed to drive a 14MHz to
18MHz series resonant crystal, see Table 6 and 7 for
more details on the crystal frequency range and
specifications.
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
12
XTAL (MHz)
Min.
f
VCO
(GHz)
Min.
Max.
X R
REF
168
Max.
14
18
2.352
3.024
Table 6. XTAL Frequency Range and Valid
Programmable Range Table
Min.
Typ.
Max.
Units
Frequency Range
(Fundamental Mode-
Series Resonant)
14
18
MHz
Frequency Tolerance
@ 25°C
±30
±50
PPM
Frequency Stability over
0°C to 70°C
±50
±100
PPM
Operating
Temperature Range
-40
+85
°C
Storage
Temperature Range
Aging (per yr/1
st
3yrs)
-55
+125
°C
±5
PPM
Equivalent Series
Resistance (ESR)
50
Drive Level
100
μW
Table 7. Quartz Crystal Oscillator Specifications
Oscillator Tips
1. Mount the crystal as close to the SY89538L
as possible to minimize parasitic effects.
2. Mount the crystal on the same plane as the
SY89538L to minimize on via hole inductance.
3. To minimize noise pick up on the loop filter
pins, cut the ground plane directly underneath
the loop filter component pads and traces.
4. Keep the crystal and its traces away from
adjacent noisy traces to minimize noise
coupling.
Figure 2 below illustrates how to interface the crystal
with the SY89538L.
Figure 2. Crystal Interface
Quartz Crystal Selection:
Note: Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron
RFCK
The input MUX drives the PLLs phase detector, which
expects a frequency between 9.325MHz and
94.5MHz. Therefore, reference clock maximum input
frequency is 756MHz when the reference divider is set
to a divide-by-8 and the reference clock minimum
frequency is 9.325MHz when the reference divider is
set to a divide-by-1. Given that the VCO frequency
range is from 2.352GHz to 3.024GHz, the minimum
and maximum frequency range of RFCK can be
calculated as follows:
Minimum Output Frequency (9.33MHz Input):
(
)
2
Pr
Pr
×
×
×
×
=
by
Div
r
PostDivide
eDivider
vider
FeedbackDi
eDivider
f
f
PHASE
OUT
(
.
) (
8
×
) ( )
×
( ) ( ) ( )
2
5
2
2
63
×
33
×
=
MHz
f
OUT
MHz
f
OUT
4
29
=
Maximum Output Frequency (756MHz Input):
(
) ( )
×
( ) ( ) ( )
2
1
2
×
2
2
8
8
756
×
×
×
=
MHz
f
OUT
MHz
f
OUT
756
=
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