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參數(shù)資料
| 型號(hào)： | SY89295UTI TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 3.2ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 3.2ns ~ 14.8ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY89295UTITR SY89295UTITR-ND |
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Micrel, Inc.
SY89295U
March 2011
8
M9999-032511
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics(7)
TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
fMAX
Maximum Operating Frequency
Clock
VOUT ≥ 400mV
1.5
GHz
tpd
Propagation Delay
IN to Q; D[0–10]=0
IN to Q; D[0–10]=1023
/EN to Q: D[0–10]=0
D10 to CASCADE
3200
11500
3400
350
4200
14800
4400
670
ps
tRANGE
Programmable Range
tpd (max.) – tpd (min)
8300
ps
tSKEW
Duty Cycle Skew
tPHL – tPLH
Note 8
25
ps
Δt
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
D0-D9 High
10
15
35
70
145
290
575
1150
2300
4610
9220
ps
INL
Integral Non-Linearity
Note 9
±10
ps
tS
Setup Time
D to LEN
D to IN
/EN to IN
Note 10
Note 11
200
350
300
ps
tH
Hold Time
LEN to D
IN to /EN
Note 12
200
400
ps
Notes:
7.
High-frequency AC electricals are guaranteed by design and characterization.
8.
Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output.
9.
INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The
maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1024. INL = measured
delay – measured minimum delay + (step number
∞ TIL).
10. This setup time defines the amount of time prior to the input signal. The delay tap of the device must be set.
11. This setup time defines the amount of the time that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater
than ±75mV to the IN, /IN transition.
12. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response
greater than ±75mV to the IN, /IN transition.
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| SY89296U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY WITH FINE TUNE CONTROL |
| SY89296U_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 1.5GHz Precision LVPECL Programmable Delay |
| SY89296UMG | 功能描述:延遲線/計(jì)時(shí)元素 2.5V/3.3V PECL Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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| SY89296UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY WITH FINE TUNE CONTROL |
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