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參數(shù)資料
| 型號： | SY89231UMG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIVIDER LVDS 16-MLF |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | Precision Edge® |
| 類型： | 時鐘除法器 |
| PLL： | 無 |
| 輸入： | CML，LVDS，PECL |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2113-5 576-2113-5-ND 576-2965-5 |
Micrel, Inc.
SY89231U
November 2007
M9999-110507-A
hbwhelp@micrel.com or (408) 955-1690
7
Functional Description
Output Duty Cycle Equation
For a non 50% input, derate the spec by:
Divide by 3:
(0.5 -
3
100
1
X
+
) x100, in %
Divide by 5:
(0.5 -
5
100
2
X
+
) x100, in %
X= input Duty Cycle, in %
Example: if a 45% input duty cycle is applied or X=45,
in divide by 3 mode, the spec would expand by 1.67%
to 44.3%-55.7%
Enable (EN)
EN is a synchronous TTL/CMOS-compatible input that
enables/disables the outputs based on the input to
this pin. Internal 25k
pull -up resistor defaults the
input to logic HIGH if left open. Input switching
threshold is VCC/2.
The Enable function operates as follows:
1.
The
enable/disable
function
is
synchronous so that the clock outputs will
be enabled following a rising and a falling
edge of the input clock when switching
from EN=LOW to EN=HIGH.
However, when switching from EN=HIGH
to EN=LOW, the clock outputs will be
disabled following an input clock rising
edge and an output clock falling edge.
2.
The
enable/disable
function
always
guarantees the full pulse width at the
output
before
the
clock
outputs
are
disabled, non-depending on the divider
Divider Operation
The divider operation uses both the rising and falling
edge of the input clock. For divide by 3, the falling
edge of the second input clock cycle will determine
the falling edge of the output. For divide by 5, the
falling edge of the third input clock cycle.
Refer to
Figure 1c.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89231UMG TR | 功能描述:時鐘驅(qū)動器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89231UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2GHz Precision, LVDS ÷3, ÷5 Clock Divider |
| SY89250V | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ENHANCED DIFFERENTIAL RECEIVER |
| SY89250VMG | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ENHANCED DIFFERENTIAL RECEIVER |
| SY89250VMG TR | 功能描述:緩沖器和線路驅(qū)動器 3.3V/5V Ultrasmall Oscillator Amplifier (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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