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參數(shù)資料
| 型號(hào)： | SY87724L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| 中文描述： | 3.3 AnyRate復(fù)用/解復(fù)用器高達(dá)2.7GHz的 |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | SY87724L |
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SY87724L
FINAL
7
Micrel
Wide Mux
The more typical case will be to convert 8 or 10 bit wide
parallel data words into a serial bit stream. Because the
worst case parallel input rate is on the order of 250 to 340
Mega-transfers per second, single ended parallel inputs are
used.
This scenario is much like the narrow mux case, except
now MPINCK+ clocks slower, for 8 or 10 bit parallel words.
MDM
MSOUT
±
MP0-9
MPINCK+
MTXCLK
±
Figure 5. Wide Mux
Note that the input data indication is now single ended,
and that completely different input pins are used, as
compared to the 4 or 5 bit case.
The following table summarizes the available bit widths.
The right column shows the parallel input bits, such as they
will appear in the serial output stream.
Width
Sequence
4
MPF0
±
, MPF1
±
, MPF2
±
, MPF3
±
MPF0
±
, MPF1
±
, MPF2
±
, MPF3
±
, MPF4
±
5
8
MP5, MP6, MP7, MP8, MP0, MP1, MP2, MP3
10
MP5, MP6, MP7, MP8, MP9, MP0, MP1, MP2, MP3,
MP4
Loopback
To ease system design, the SY87724L MDM has the
capability to loop parallel data in, through the mux, into the
demux, and back to parallel data out. This permits system
check-out through to the individual MDM device. Note that,
for a full check-out, some form of loopback further down the
serial stream is required.
Loopback is incorporated into MDM by modifying the
serial clock, data, and sync inputs to the demux stage.
During loopback, the source of serial information for the
demux is changed. The MSOUT
±
,
MTXCLK
±
and
MSYNOUT
±
are internally muxed to the DSIN
±
, DCKIN
±
,
and DFMIN
±
nodes of the demux section. The MSYNOUT
±
signal
has
the same characteristics as the DFMIN logic
expects.
This exercises the internal data path, both mux and
demux, for MDM, and also the control logic. The parallel
data presented to the parallel inputs will appear, some small
but unspecified time later, at the parallel outputs.
MSOUT
±
DFMIN
±
MP*
DP*
* Number of wires depends on the SIZX bits.
DCKIN
±
DSIN
±
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY87724LH1 | 3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY88702 | High Efficient Rectifier Diodes |
| SY88703V | High Efficient Rectifier Diodes |
| SY88722V | High Efficient Rectifier Diodes |
| SY88793V | High Efficient Rectifier Diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87724L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724LE | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate?? MUX/DEMUX Up to 2.7GHz |
| SY87724LH1 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724LHEI | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
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