參數(shù)資料
型號(hào): SY87724L
廠商: Micrel Semiconductor,Inc.
英文描述: 3.3V AnyRate MUX/DEMUX Up to 2.7GHz
中文描述: 3.3 AnyRate復(fù)用/解復(fù)用器高達(dá)2.7GHz的
文件頁(yè)數(shù): 4/13頁(yè)
文件大?。?/td> 103K
代理商: SY87724L
SY87724L
FINAL
4
Micrel
PIN CONFIGURATION
1
80-PIN
LQFP-PQ2
2
3
4
5
6
7
8
9
10
11
12
13
21 22 23 24 25 26 27 28 29 30 31 32 33
60
59
58
57
56
55
54
53
52
51
50
49
48
77 76 75 74 73 72 71 70 69 68 67 66 65
GND
VCC
NC
NC
NC
SIZ0
SIZ1
SIZ2
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
VCC
VCCO
14
15
16
47
46
45
78
79
80
34 35 36
M
N
VCCO
17
18
19
20
37 38 39 40
44
43
42
41
64 63 62 61
N
G
M
M
L
V
N
N
M
M
V
D
D
D
D
G
V
V
G
DCKIN+
DCKIN
VCCO
DP9
DP8
DP7
DP6
DP5
DP4
DP4+
DP3
DP3+
VCCO
VCCO
DP2
DP2+
DP1
DP1+
VCC
M
G
M
M
M
M
M
M
M
M
M
M
V
G
V
D
D
D
D
PIN NAMES
COMMON
LPBK
TTL Input
This pin defines whether a device exhibits local loopback
or not, as per the following table. Loopback internally
connects mux serial out to demux serial in, thus the user
may expect mux side parallel data to appear on the demux
parallel output pins.
LPBK
0
1
Functioning
Loopback
Normal
SIZ0, SIZ1, SIZ2
TTL Input
These three signals determine the width of the parallel
output, as well as the width of parallel input. The following
table describes the parallel width options.
Width
4
5
8
10
Undefined
SIZ0
0
1
0
1
X
SIZ1
0
0
1
1
X
SIZ2
(1)
0
0
0
0
1
Note:
1. Pin 8 (SIZ2) should always be tied to a TTL logic level LOW.
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