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參數(shù)資料
| 型號(hào)： | SY87702LHI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | AnyRate® |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | PECL |
| 輸出： | CML，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.5Gbps |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-EP-TQFP |
| 包裝： | 托盤 |
SY87702L
6
Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
FREQSEL1, ..., FREQSEL3 [Frequency Select] – TTL
Inputs
These inputs select the output clock frequency range, as
shown in Table 2.
VCOCLK
FREQSEL1
FREQSEL2
FREQSEL3
Divider
00
0
1
00
1
2
01
0
4
01
1
6
10
0
8
10
1
12
11
0
16
11
1
24
Table 2.
DIVSEL1, ..., DIVSEL3 [Divider Select] – TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in Table 3. Please note that the divide by 32
selection, “011”, is only available for use when FREQSEL
are set to “000.”
REFCLK
DIVSEL1
DIVSEL2
DIVSEL3
Multiplier
00
0
1
00
1
2
01
0
4
01
1
32
10
0
8
10
1
10
11
0
16
11
1
20
Table 3.
CLKSEL [Clock Select] – TTL Input
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
ENPECL [Enable PECL] – TTL Input
This input, when HIGH (ENPECL = 1), enables the
differential PECL outputs TCLKE± RDOUTE±, and RCLKE±.
It also disables the CML outputs, by setting TCLKC+,
RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC–,
RDOUTC–, and RCLKC– logic LOW.
When set LOW (ENPECL = 0), this signal enables the
differential CML outputs TCLKC±, RDOUTC±, and RCLKC±.
It also disables the PECL outputs by setting TCLKE+,
RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE–,
RDOUTE–, and RCLKE– logic LOW.
OUTPUTS
LFIN [Link Fault Indicate] – O.C. TTL Output
This output indicates the status of the input data stream
RDIN. LFIN will go HIGH if CD is HIGH and RDIN is within
the frequency range of the Receive PLL (as per ALRSEL).
LFIN is an asynchronous output.
RDOUTE
± [Receive Data Out] – Differential PECL
These ECL 100K outputs represent the recovered data
from the input data stream (RDIN). This recovered data is
sampled on the falling edge of RCLK.
RDOUTC
± [Receive Data Out] – Differential CML
This is the CML version of RDOUTE±.
RCLKE
± [Receive Clock Out] – Differential PECL
These ECL 100K outputs represent the recovered clock
used to sample the recovered data (RDOUT).
RCLKC
± [Receive Clock Out] – Differential CML
This is the CML version of RCLKE±.
TCLKE
± [Transmit Clock Out] – Differential PECL
These ECL 100K outputs represent either the recovered
clock (CLKSEL = HIGH) used to sample the recovered data
(RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
TCLKC
± [Transmit Clock Out] – Differential CML
This is the CML version of TCLKE±.
INPUTS/OUTPUTS
PLLSN+, PLLSN– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis narrow-
band PLL.
PLLSW+, PLLSW– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis wide-band
PLLs.
PLLRN+, PLLRN– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery narrow-
band PLL.
PLLRW+, PLLRW– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery wide-band
PLLs.
OTHERS
VCC
Supply Voltage
VCCO
Output Supply Voltage
VCCA
Analog Supply Voltage
GND
Ground
GNDA
Analog Ground
NC
These pins are for factory test, and are to be
left unconnected during normal use.
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| SY87721LHG | 功能描述:IC CLOCK/DATA RECOVERY 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:AnyRate® 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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