hbwhelp@micrel.com or (408) 955-1690 4 Pin Description" />
參數(shù)資料
型號: SY58621LMG TR
廠商: Micrel Inc
文件頁數(shù): 15/20頁
文件大?。?/td> 0K
描述: TXRX 3.2GBPS CML/LVPECL 24-MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: SY58
邏輯類型: CML/LVPECL 背板收發(fā)器,帶集成環(huán)回
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,24-MLF?
供應(yīng)商設(shè)備封裝: 24-MLF?(4x4)
包裝: 帶卷 (TR)
其它名稱: SY58621LMGTR
SY58621LMGTR-ND
Micrel, Inc.
SY89465U
August 2010
M9999-080510-C
hbwhelp@micrel.com or (408) 955-1690
4
Pin Description (Continued)
Pin Number
Pin Name
Pin Function
42
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer.
Note that this input is internally connected to a 25k pull-up resistor and will default
to logic HIGH state if left open. VTH = VCC/2.
1, 11, 6
GND,
Exposed Pad
Ground: Ground and exposed pad must be connected to the same ground plane.
12
CAP
Power-on-Reset (POR) initialization capacitor. When using the multiplexer with RPE
capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal
RPE logic starts up in a known state. See “Power-On Reset (POR) Description”
section for more details regarding capacitor selection. If this pin is tied directly to VCC,
the RPE function will be disabled and the multiplexer will function as a normal
multiplexer. The CAP pin should never be left open or tied directly to GND.
14
EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9 outputs.
It is internally connected to a 25k pull-up resistor and will default to a logic HIGH
state if left open. When disabled, CLK output goes LOW and /CLK goes HIGH. EN
being synchronous, outputs will be enabled/disabled when they are in LOW state.
Thus, a runt pulse is avoided if the device is enabled/disabled by an asynchronous
control. VTH = VCC/2.
Truth Table
Inputs
Outputs
IN0
/IN0
IN1
/IN1
SEL
Q
/Q
0
1
X
0
1
0
X
0
1
0
X
0
1
0
1
X
1
0
1
0
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