參數(shù)資料
型號(hào): SY54016RMG TR
廠商: Micrel Inc
文件頁數(shù): 3/13頁
文件大小: 0K
描述: IC RCVR/LINE DVR CML LV 8-MLF
產(chǎn)品培訓(xùn)模塊: High Bandwidth Product Overview
標(biāo)準(zhǔn)包裝: 1
邏輯類型: 差分接收器/驅(qū)動(dòng)器
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤,8-MLF?
供應(yīng)商設(shè)備封裝: 8-MLF?(2x2)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1088 (CN2011-ZH PDF)
其它名稱: 576-3069-6
Micrel, Inc.
SY89464U
December 2007
M9999-120607-B
hbwhelp@micrel.com or (408) 955-1690
11
Case #4: Input Clock Failure: Switching from the
selected clock input stuck in an undetermined state to
a valid clock input (RPE-enabled).
If CLK1 fails to an undetermined state (e.g., amplitude
falls below the 100mV (VIN) minimum single-ended
input limit, or 200mV differentially) before the RPE
MUX selects CLK2 (using the SEL pin), the switchover
to the valid clock CLK2 will occur either following Case
#2 or Case #3, depending upon the last valid state at
the CLK1.
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent duty
cycle distortions or runt pulses in case of a slowly
deteriorating (but still toggling) input signal. Due to the
FSI function, the propagation delay will depend upon
rise and fall time of the input signal and on its
amplitude. Refer to “Typical Operating Characteristics”
for detailed information.
Timing Diagram 4
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