ZO
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� SY100EP195VTG
寤犲晢锛� Micrel Inc
鏂囦欢闋佹暩(sh霉)锛� 3/18闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC DELAY LINE 1024TAP 32-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 250
绯诲垪锛� 100EP, ECL Pro®
妯�(bi膩o)鐗�/姝ョ礆(j铆)鏁�(sh霉)锛� 1024
鍔熻兘锛� 鍙法绋�
寤堕伈鍒扮涓€鎶介牠锛� 2.05ns
鎺ラ牠澧為噺锛� 10ps
鍙敤鐨勭附寤堕伈锛� 2.05ns ~ 12.2ns
鐛�(d煤)绔嬪欢閬叉暩(sh霉)锛� 1
闆绘簮闆诲锛� 3 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 32-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 32-TQFP
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 1088 (CN2011-ZH PDF)
鍏跺畠鍚嶇ū锛� 576-1993-5
SY100EP195VTG-ND
11
ECL Pro
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
R2
82
R2
82
ZO = 50
+3.3V
Vt = VCC 鈥�2V
R1
130
R1
130
+3.3V
Figure 6a. Parallel Termination鈥擳hevenin Equivalent
Note:
1. For +5.0V systems: R1 = 82, R2 = 130.
Z = 50
50
+3.3V
鈥淪ource鈥�
鈥淒estination鈥�
Rb
C1 (optional)
0.01F
Figure 6b. Three-Resistor 鈥淵-Termination鈥�
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46 to 50. For +5V systems, Rb = 110.
+3.3V
ZO = 50
R2
82
+3.3V
R1
130
R1
130
R2
82
Vt = VCC 鈥�2V
Q
/Q
50
+3.3V
0.01F
VBB
Figure 6c. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. Micrel's differential I/O logic devices include a VBB reference pin .
3. Connect unused input through 50 to VBB. Bypass with a 0.01F capacitor to VCC, not GND, as PECL is referenced to VCC.
TERMINATING PECL
鐩搁棞(gu膩n)PDF璩囨枡
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