參數(shù)資料
型號: SY100EP196VTG
廠商: Micrel Inc
文件頁數(shù): 1/18頁
文件大?。?/td> 0K
描述: IC DELAY LINE 1024TAP 32-TQFP
標準包裝: 250
系列: 100EP, ECL Pro®
標片/步級數(shù): 1024
功能: 可編程
延遲到第一抽頭: 2.05ns
接頭增量: 10ps
可用的總延遲: 2.05ns ~ 12.2ns
獨立延遲數(shù): 1
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 1088 (CN2011-ZH PDF)
其它名稱: 576-2462
SY100EP196VTG-ND
1
ECL Pro
SY100EP196V
Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
■ Pin-for-pin, plug-in compatible to the ON
Semiconductor MC100EP196
■ Maximum frequency > 2.5GHz
■ Programmable range: 2.2ns to 12.2ns
■ 10ps increments
■ 30ps fine tuning range
■ PECL mode operating range: V
CC = 3.0V to 5.5V
with VEE = 0V
■ NECL mode operating range: V
CC = 0V
with VEE = –3.0V to –5.5V
■ Open input default state
■ Safety clamp on inputs
■ A logic high on the /EN pin will force Q to logic low
■ D[0:10] can accept either ECL, CMOS, or TTL inputs
■ V
BB output reference voltage
■ Available in a 32-pin TQFP package
FEATURES
3.3V/5V 2.5GHz PROGRAMMABLE
DELAY WITH FINE TUNE CONTROL
ECL Pro
SY100EP196V
APPLICATIONS
■ Clock de-skewing
■ Timing adjustment
■ Aperture centering
Rev.: E
Amendment: /0
Issue Date:
July 2006
Micrel Semiconductor
ON Semiconductor
SY100EP196VTI
MC100EP196FA
SY100EP196VTITR
MC100EP196FAR2
CROSS REFERENCE TABLE
The SY100EP196V is a programmable delay line, varying
the time a logic signal takes to traverse from IN to Q. This
delay can vary from about 2.2ns to about 12.2ns. The input
can be PECL, LVPECL, NECL, or LVNECL.
The delay varies in discrete steps based on a control
word presented to SY100EP196V. The 10-bit width of this
latched control register allows for delay increments of
approximately 10ps. In addition, delay may be varied
continuously in about a 30ps range by setting the voltage at
the FTUNE pin.
An eleventh control bit allows the cascading of multiple
SY100EP196V devices, for a wider delay range. Each
additional SY100EP196V effectively doubles the delay range
available.
For maximum flexibility, the control register interface
accepts CMOS or TTL level signals, as well as the input
level at the IN± pins.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
TYPICAL APPLICATIONS CIRCUIT
TYPICAL PERFORMANCE
IN
CONTROL
LOGIC
Data Signal
of Unknown Phase
CLOCK+
CLOCK–
/IN
Q
/Q
FTUNE
D
CK
Q+
Q–
D[9:0]
SY100EP196V
Flip-Flop
Fine Tune Voltage
0
2000
4000
6000
8000
10000
12000
0
200 400 600 800 1000 1200
DELAY
(ps)
TAP (DIGITAL WORD)
Delay vs. Tap
ECL Pro is a registered trademark of Micrel, Inc.
ECL Pro
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