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參數(shù)資料
| 型號： | SY05-HF |
| 廠商： | Raltron Electronics Corporation |
| 英文描述： | SYNCHRONOUS EQUIPMENT MULTI OUTPUT HIGH FREQUENCY HITLESS SWITCHING |
| 中文描述： | 同步設(shè)備多輸出的高頻過沖切換 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 198K |
| 代理商： | SY05-HF |
SYNCHRONOUS EQUIPMENT
MULTI OUTPUT HIGH FREQUENCY HITLESS SWITCHING
- SY05-HF
RALTRON ELECTRONICS CORP.
!
10651 N.W.19
th
St
!
Florida 33172
!
U.S.A.
Tel: 305 593-6033
!
Fax: 305-594-3973
!
e-mail: sales@raltron.com
!
Internet: http://www.raltron.com
Pin
#
Name
Description
Signal
Technology
VL
VH/ DC Voltage
Typ
5.0**
(3.3)
5.0**
(3.3)
5.0**
(3.3)
------
Vcc-1.025
Vcc-1.025
5.0
(3.3)
----
Min
-----
Typ
-----
Max
-----
Min
4.75**
(3.135)
4.5**
(2.97)
4.5**
(2.97)
------
Vcc-1.085
Vcc-1.085
4.5
(2.97)
(2.97)
Max
5.25**
(3.465)
5.25**
(3.465)
5.25**
(3.465)
------
Vcc-0.885
Vcc-0.885
5.25
(3.465)
----
1
+Vcc
Positive Voltage Supply
DC
2
REF1 FR
Reference 1 Freerun Input -> the signal High (“1” logic) FREERUN comes from Clock Unit 1
DC
0
0.25 **
(0.15)
0.25 **
(0.15)
-----
Vcc-1.620
Vcc-1.620
0.25 (0.15)
0.5**
(0.3)
0.5**
(0.3)
----
Vcc-1.56
Vcc-1.56
0.5
(0.3)
4.5**
3
REF2 FR
Reference 2 Freerun Input -> the signal High (“1” logic) FREERUN comes from Clock Unit 2
DC
0
4
5
6
GND
OUT 1
OUT 1
Ground
Synchronized Output 1 -> the output of the synchronized signal.
Synchronized Complementary Output 1 -> the output of the synchronized signal.
Alarm signal out -> the output is high when the module is unlocked (“1” logic)
-----
-----
LV/PECL
LV/PECL
DC
Vcc-1.680
Vcc-1.680
0
7
ALARM
HCMOS
(3.3 Tolerable)
0
-----
0.5**
(0.3)
8
OUT 2
Buffered reference or synchronized signal Output 2 ->
a buffered external reference Signal (LVCMOS)
or
a buffered synchronized local oscillator signal. (LVPECL)
Buffered reference or synchronized complimentary signal Output 6 ->
a buffered external reference Signal (LVCMOS)
or
a buffered synchronized local oscillator signal. (LVPECL- complimentary).
Ground
Divider Output 3 -> the output of the synchronized signal divided by 2;
Complementary Divider Output 3 -> the output of the synchronized signal divided by 2
Divider Output 4 -> the output of the synchronized signal divided by 4.
Complementary Divider Output 4 -> the output of the synchronized signal divided by 4
. –
Divider Output 5 -> the output of the synchronized signal divided by 8;
Complementary Divider Output 5 -> the output of the synchronized signal divided by 8;
Ground
Control Input 2 -> the external input for selecting mode of the unit – see table.
LV/PECL
Vcc-1.680
Vcc-1.620
Vcc-1.56
Vcc-1.085
Vcc-1.025
Vcc-0.885
HCMOS
(3.3 Tolerable)
0
-----
0.5**
(0.3)
4.5**
(2.97)
----
----
9
OUT 6
LV/PECL
Vcc-1.180
Vcc-1.135
Vcc-
0.975
----
Vcc-1.56
Vcc-1.56
Vcc-1.56
Vcc-1.56
Vcc-1.56
Vcc-1.56
----
0.5**
(0.3)
0.5**
(0.3)
0.5**
(0.3)
0.5**
(0.3)
0.5**
(0.3)
0.5**
(0.3)
----
0.25
**
(0.15)
0.25
**
(0.15)
0.5**
(0.3)
0.5**
(0.3)
0.5**
(0.3)
0.5**
(0.3)
Vcc-1.56
Vcc-1.56
0.5**
(0.3)
----
Vcc-1.085
Vcc-1.025
Vcc-
0.880
------
Vcc-0.885
Vcc-0.885
Vcc-0.885
Vcc-0.885
Vcc-0.885
Vcc-0.885
------
5.25**
(3.465)
5.25**
(3.465)
5.25**
(3.465)
5.25**
(3.465)
5.25**
(3.465)
5.25**
(3.465)
------
5.0**
(3.3)
10
11
12
13
14
15
16
17
GND
OUT 3
OUT 3
OUT 4
OUT 4
OUT 5
OUT 5
GND
-----
-----
-----
------
------
LV/PECL
LV/PECL
LV/PECL
LV/PECL
LV/PECL
LV/PECL
-----
DC
Vcc-1.680
Vcc-1.680
Vcc-1.680
Vcc-1.680
Vcc-1.680
Vcc-1.680
-----
Vcc-1.620
Vcc-1.620
Vcc-1.620
Vcc-1.620
Vcc-1.620
Vcc-1.620
-----
0.25 **
(0.15)
0.25 **
(0.15)
0.25 **
(0.15)
0.25 **
(0.15)
0.25 **
(0.15)
0.25 **
(0.15)
-----
Vcc-1.085
Vcc-1.085
Vcc-1.085
Vcc-1.085
Vcc-1.085
Vcc-1.085
------
4.5**
(2.97)
4.5**
(2.97)
4.5**
(2.97)
4.5**
(2.97)
4.5**
(2.97)
4.5**
(2.97)
------
0.5**
(0.3)
Vcc-1.025
Vcc-1.025
Vcc-1.025
Vcc-1.025
Vcc-1.025
Vcc-1.025
------
5.0**
(3.3)
5.0**
(3.3)
5.0**
(3.3)
5.0**
(3.3)
5.0**
(3.3)
5.0**
(3.3)
------
4.5**
(2.97)
18
CNT 2
0
19
CNT 1
Control Input 1 -> the external input for selecting mode of the unit – see table.
DC
0
20
AUTO/MAN
Auto/Manual configuration input -> selection input for operating mode
Man=”0” ; Auto = “1”
Reference 2 Holdover Input -> the signal High (“1” logic) HOLDOVER comes from Clock Unit
2
Reference 1 Holdover Input -> the signal High (“1” logic) HOLDOVER comes from Clock Unit
1
Revert / Non revert input-> selection input for revert feature
Revertive-“1” ; Non-Revertive = “0”
Ground
Reference 2 Alarm Input -> the signal High (“1” logic) ALARM OUT comes from Clock Unit 2
DC
0
21
REF2 HL
DC
0
22
REF1 HL
DC
0
23
RV/NRV
DC
0
24
GND
-----
DC
-----
0
25
REF2 AL
0
26
REF1 AL
Reference 1 Alarm Input -> the signal High (“1” logic) ALARM OUT comes from Clock Unit 1
DC
0
0
0.5**
(0.3)
4.5**
(2.97)
5.0**
(3.3)
27
EX REF 2
External Reference 2 Input -> the input signal from reference 2
HCMOS
(3.3 Tolerable)
DC
0
-----
4.5**
(2.97)
4.5**
(2.97)
4.5**
(2.97)
4.5**
(2.97)
Vcc-1.085
Vcc-1.085
4.5**
(2.97)
------
----
----
28
REF2 UL
Reference 2 Unlocked Input -> the signal High (“1” logic) PLL UNLOCK comes from Clock
Unit 2
External Reference 1 Input -> the input signal from reference 1
0
0.25 **
(0.15)
-----
5.0**
(3.3)
----
5.25**
(3.465)
----
29
EX REF 1
HCMOS
(3.3 Tolerable)
DC
0
30
REF1 UL
Reference 1 Unlocked Input -> the signal High (“1” logic) PLL UNLOCK comes from Clock
Unit 1
Time Loop back Reference Input -> the input from time loopback
Time Loop back Complementary Input -> the complementary input from time loopback
Time Loop back OK (nput -> When high (“1” logic) the loop back reference is valid for use
0
0.25 **
(0.15)
Vcc-1.620
Vcc-1.620
0.25 **
(0.15)
-----
5.0**
(3.3)
Vcc-1.025
Vcc-1.025
5.0**
(3.3)
------
5.25**
(3.465)
Vcc-0.885
Vcc-0.885
5.25**
(3.465)
------
31
32
TLB REF
TLB REF
LV/PECL
LV/PECL
DC
Vcc-1.680
Vcc-1.680
33
TLB OK
0
34
GND
Ground
-----
-----
For other pin-out configurations contact the factory!
**
Indicates corresponding values to Vcc=5V
ORDERING INFORMATION
Please contact factory with input/output options for P/N assiagnment.
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