www.semtech.com/products/ Page 18 ADVANCED COMMUNICATIONS & SENSING DATASHEET SX8725C ZoomingADC fo" />
參數(shù)資料
型號： SX8725CWLTDT
廠商： Semtech
文件頁數(shù)： 10/68頁
文件大?。?/td> 0K
描述： IC DAS ADC 16BIT I2C/SRL
標(biāo)準(zhǔn)包裝： 1
系列： ZoomingADC™
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
輸入類型： 差分
輸出類型： 數(shù)字
接口： I²C
安裝類型： 表面貼裝
封裝/外殼： 12-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 12-MLPD-EP（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： SX8725CWLTDTDKR
www.semtech.com/products/
Page 18
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8725C
ZoomingADC for sensing data acquisition
Revision 1.01
January 2011
Semtech
7 ZoomingADC
7.1 Overview
The ZoomingADC is a complete and versatile low-power analog front-end interface typically intended for sensing
applications. In the following text the ZoomingADC will be referred as ZADC.
The key features of the ZADC are:
Programmable 6 to 16-bit dynamic range over-sampled ADC
Flexible gain programming between 1/12 and 1000
Flexible and large range offset compensation
Differential or single-ended input
2-channel differential reference inputs
Power saving modes
The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an over sampled
A/D converter. The reference voltage can be selected on two different channels. Two offset compensation amplifiers
allow for a wide offset compensation range. The programmable gain and offset allow the application to zoom in on a
small portion of the reference voltage defined input range.
7.1.1 Acquisition Chain
Figure 10, page 18 shows the general block diagram of the acquisition chain (AC). A control block (not shown in
Figure 10) manages all communications with the I2C peripheral. The clocking is derived from the internal 4 MHz
Oscillator.
Analog inputs can be selected through an 8 input multiplexer, while reference input is selected between two
differential channels. It should however be noted that only 7 acquisition channels (including the VREF) are available
when configured as single ended since the input amplifier is always operating in differential mode with both positive
and negative input selected through the multiplexer.
Figure 10. ZADC General Functional Block Diagram
PGA1
PGA2
PGA3
ADC
±Vin
±Voff
±Vref
AMUX
Analog
Inputs
VMUX
Reference
Inputs
VIN
VD1
VD2
VIN,ADC
VREF,ADC
VSS
VREF
AC2
AC3
N.C.
VSS
VBATT
VSS
VREF
ANALOG ZOOM
S
Not
Recommended
for
New
Designs
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