參數(shù)資料
型號(hào)： SX8723E083TDT
元件分類(lèi)： ADC
英文描述： 5-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO12
封裝： 4 X 4 MM, ROHS COMPLIANT, MLPD-12
文件頁(yè)數(shù)： 19/53頁(yè)
文件大?。?/td> 3978K
代理商： SX8723E083TDT
ADVANCED COMMUNICATIONS & SENSING
V1.8 2009 Semtech Corp.
www.semtech.com
26
SX8723
ZoomingADC for Pressure and Temperature Sensing
Output Code Format
The ADC output code is a 16-bit word in two's complement format (see Table 15). For input voltages outside the
range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions
smaller than 16 bits, the non-significant bits are forced to the values shown in Table 16. The output code,
expressed in LSBs, corresponds to:
OSR
V
OUT
ADC
REF
ADC
IN
ADC
1
2
,
16
+
=
(LSB)
Equation 17
Recalling equation 9, this can be rewritten as:
OSR
V
GDoff
GD
V
OUT
IN
ADC
REF
TOT
ADC
REF
IN
ADC
1
2
,
16
+
=
(LSB)
Equation 18
where, from Equation 10and Equation 11, the total PGA gain and offset are respectively:
1
2
3
GD
TOT
=
(V/V)
and:
2
3
GDoff
GD
GDoff
TOT
+
=
(V/V)
ADC Input Voltage VIN,ADC
% of Full Scale (FS)
Output in LSBs
Output Code in Hex
+2.46146V
+0.5
FS
+215-1=+32'767
7FFF
+2.46138V
...
+215-2=+32'766
7FFE
...
+75V
...
+1
0001
0V
0
0000
-75V
...
-1
8FFF
...
-2.46146V
...
-215-1=-32'767
8001
-2.46154V
-0.5
FS
-215=-32'768
8000
Table 15 - Basic ADC Relationships (example for: VREF,ADC = 5V, OSR = 64, n = 16 bits)
SET_OSR[2:0]
SET_NELC = 00
SET_NELC = 01
SET_NELC = 10
SET_NELC = 11
000
1000000000
100000000
10000000
1000000
001
10000000
1000000
100000
10000
010
100000
10000
1000
100
011
1000
100
10
1
100
10
1
-
101
-
110
-
111
-
Table 16 - Last Forced LSBs in Conversion Output Registers for Resolution Settings Smaller than 16
bits (n < 16) (RegACOutMsb[7:0] & RegACOutLsb[7:0])
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