www.semtech.com/products/ Page 15 ADVANCED COMMUNICATIONS & SENSING DATASHEET SX8723C ZoomingADC fo" />
參數(shù)資料
型號(hào)： SX8723CWLTDT
廠商： Semtech
文件頁(yè)數(shù)： 7/67頁(yè)
文件大?。?/td> 0K
描述： IC DAS ADC 16BIT I2C/SRL
標(biāo)準(zhǔn)包裝： 1
系列： ZoomingADC™
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
輸入類型： 差分
輸出類型： 數(shù)字
接口： I²C
安裝類型： 表面貼裝
封裝/外殼： 12-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 12-MLPD-EP（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： SX8723CWLTDTDKR
www.semtech.com/products/
Page 15
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8723C
ZoomingADC for sensing data acquisition
Revision 1.01
January 2011
Semtech
6.3 GPIO
The GPIO block is a multipurpose 2 bit input/output port. In addition to digital behavior, D0 and D1 pins can be
programmed as analog pins in order to be used as output (reference voltage monitoring) and input for an external
reference voltage (For further details see Figure 6, Figure 7, Figure 8 and Figure 9). Each port terminal can be
individually selected as digital input or output.
The direction of each bit within the GPIO block (input only or input/output) can be individually set using the bits of the
RegOut (address 0x40) register. If D[x]Dir = 1, both the input and output buffer are active on the corresponding GPIO
block pin. If D[x]Dir= 0, the corresponding GPIO block pin is an input only and the output buffer is in high impedance.
After power on reset the GPIO block pins are in input/output mode (D[x]Dir are reset to 1).
The input values of GPIO block are available in RegIn (address 0x41) register (read only). Reading is always direct - there
is no debounce function in the GPIO block. In case of possible noise on input signals, an external hardware filter has to
be realized. The input buffer is also active when the GPIO block is defined as output and the effective value on the pin
can be read back.
Data stored in the LSB bits of RegOut register are outputted at GPIO block if D[x]Dir= 1. The default values after power
on reset is low (0).
The digital pins are able to deliver a driving current up to 8 mA.
When the bits VrefD0Out and VrefD1In in the RegMode (address 0x70) register are set to 1 the D0 and D1 pins digital
behavior are automatically bypassed in order to either input or output the voltage reference signals.
Figure 4. GPIO bloc diagram
RegOut[4]
RegOut[5]
RegOut[0]
RegIn[0]
RegOut [1]
RegIn [1]
VBG
+
-
D1/VREF
D0/VREF
RegMode [0]
0
1
RegMode[1]
0
1
0
1
ZoomingADC
IN
OUT
VREF
Internal
Bandgap
reference
1.22V
Not
Recommended
for
New
Designs
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