
2.2.1 - Address Map
PAGE
: ROW0
ROW1
.........
ROW10 : STRU[7:6] = 0 or 1 - BUF[11:8]= 10 - DEPL[3:0]from 0 t0 27
ROWATTRIBUTES : STRU[7:6]= 11 - BUF[11:8] = 0 - DEPL[4:0]from 0 to 10
REGISTERS
: STRU[7:6]= 11 - BUF[11:8] = 0
DEPL[4:0]= 12 for ZOOM register,13 for COLOR register,
14 for CONTROL register, 15 for POSITIONregister,
16 for MODE register
: STRU[7:6] = 0 or 1 - BUF[11:8]= 0 - DEPL[4:0]from 0 to 27
: STRU[7:6] = 0 or 1 - BUF[11:8]= 1 - DEPL[4:0]from 0 to 27
: .................
.....................
................
2.3 - Initializationand Down-loading Sequence
It is important that the STV5730is correctly reset
and initialized after the circuit is powered prior to
any writing. This routine is shown in Figure 3. The
two initialization bytes (00db 1000) must procede
theresetinstruction(x2)everytimeitistransmitted.
RESET & INITIALIZE
3000H
3000H
00dbH
1000H
Set Row Attributes
* 0 to 10
STOP
Next Page
Write
Set Control Registers
* Zoom
* Color
* Control
* Position
* Mode
Set RAM Attributes
i.e. TEXT PAGE
* Write Pointer
* Data
* etc.
5
Figure3
3 - THE LINE LOCKED PLL
The PLLfrequencyis 504* f
H
= 7.875MHz.
3.1 - Mixed Mode Behavior
In mixed mode,the internalPLLisline lockedto the
incoming CVBSsignal.The synciseitherextracted
bythe STV5730(if C7controlbitis set) orprovided
by the application in a composite form on the
CSYNC pin (if C7 control bit is cleared). The
STV5730separatestheverticalsyncfromthecom-
posite synchronism.
The STV5730 PLL features built-in protection
mechanismsagainstmissing andparasitichorizon-
tal sync pulses. These mechanisms are activated
once the loop is locked.
The STV5730 PLL is also insensitive to the head
switching disturbing the synchronism in the VTR
applications(playback).
Themissingpulsesmaybedetected.The M1mode
bitenables the detection.
In addition,the BAR input pin is available to enter
a signal that forces the PLLin free run mode. This
capabilitymay be used for search mode in VTRs,
to improve the loop robustness against the noise
bar.The BAR inputis enabledby the M0 mode bit.
3.2 - Horizontal Sync Re-insertion
This mechanism is of interest in mixed mode, to
cancelthetexthorizontaljitter whenthesyncsignal
is too bad. It is activated by the M4 mode bit and
must be turned off in full page mode.
The active part of the line is protected against
parasiticsyncinsertion.The modified syncisactive
on all output pins (ie CSYNC if C7 is set, VIDEO
OUT1, VIDEO OUT2).
Ajitter greaterthan 0.42useccannot be cancelled.
An ease useof thesynchronism re-insertion capa-
bility is to have it always active in mixed mode.
3.3 - FullPage Mode Behavior
Inthiscase,thePLLislockedonaninternal64usec
referencederived from the 4*fsc quartz.
The STV5730 generatesa noninterlace output.
4 - MUTE
The STV5730 monitors the sync to determine
whetherit is a stable signal or not.
MUTE = high : no stablesignal
MUTE = low: stable CVBS input signal
STV5730
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