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參數(shù)資料
| 型號： | STV5404E-001 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Mono and Colour Digital Video CMOS Image Sensors |
| 中文描述： | 莫諾和數(shù)字視頻彩色CMOS圖像傳感器 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 786K |
| 代理商： | STV5404E-001 |
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VV5404 & VV6404
CD5404-6404F-A
22/54
4.6.4
For successfully entry and exit into and out of low power and ‘sleep’ modes the system clock, CLKI, must remain
active for the duration of these modes.
Application of the system clock during sensor low-power modes
4.7
There are two distinct ways for qualifying the data nibbles appearing of the output data bus
Qualification of Output Data
4.7.1 Using the External Clock signal applied to CKI
The data on the output data bus, changes on the rising edge of CKI. The delay between the video processor supplying
a rising clock edge and the data on the databus becoming valid, depends on the length of the cable between the
sensor and the video processor. To allow the video processor to find the best sampling position for the data nibbles,
via the serial interface the databus can be forced to output continuously 9
H
, 6
H
, 9
H
, 6
H
,...
4.7.2
VV6404 provides a data qualification clock for the output bus. There are two frequencies for the qualification clock:
one runs at the nibble rate and the other at the pixel read-out rate. The falling edge of the fast QCK qualifies every
nibble irrespective of whether it is most or least significant nibble. For the slow QCK, the rising edge qualifies the most
significant nibbles in the output data stream and the falling edge qualifies the least significant nibbles in the output
data stream.
There are 4 modes of operation of QCK.
1. Disabled (Always low - (Default)
2. Free running - qualifies the whole of the output data stream.
3. Embedded control sequences, status data and pixel data.
4. Pixel Data Only.
The operating mode for QCK is set via the serial interface. The QCK output is tristated when OEB is high.In one of
the modes available via the serial interface the slow version of QCK will appear on the QCK pin while the fast version
of the same signal will appear on the FST pin.
In the case where the border rows and columns are disabled, there is simply no qualification pulse at that point in time
i.e. when pixels 0,1, 354 and 355 are normally output.
The QCK pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor
to control external devices, e.g. stepper motors, shutter mechanisms. The configuration details for QCK can be found
in sections 5.5.7 and 5.5.8 of this document.
Data Qualification Clock, QCK
4.7.3
There are 3 modes of operation for the FST pin programmable via the serial interface:
1. Disabled (Always Low- Default).
2. Frame start signal. The FST signal occurs once frame, is high for 356 pixel periods (712 system clock periods)
and qualifies the data in the start of frame line.
The FST is tristated when OEB is high.
The FST pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor
to control external devices, e.g. stepper motors, shutter mechanisms.
The configuration details for FST can be found in sections 5.5.7 and 5.5.8 of this document.
Frame Start Signal, FST
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