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參數(shù)資料
| 型號： | STV0502 |
| 廠商： | 意法半導體 |
| 英文描述： | CCD SENSORS ANALOG PROCESSOR IC |
| 中文描述： | CCD傳感器模擬處理器IC |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 158K |
| 代理商： | STV0502 |
ELECTRICAL CHARACTERISTICS
T
amb
= 25
o
C, V
DD
= V
CC
= 5V, unless otherwise specified (continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
8 BITS ADC & OB CLAMP
OB_rise
OB_decay
BLK_RAN
OB High Time Constant
OB Low Time Constant
Black Level Adjust Range
Pin 38, OB 0 to 1
Pin 38, OB 1 to 0
Pins 8 to 15, OB high,
Serial bus from H00 to H1F
Pins 8 to 15, per serial bus LSB step
Pins 8 to 15
Bus = H00
Bus = H1F
Pin 38 test signal above black
clamping level (V
BOT
)
Pin 24
From a sampling to data out
4
mV/
μ
s
mV/ms
LSBs
-2
31
BLK_res
BLK_LEV
Black Level Adjust Resolution
Black Level Adjust
1
LSBs
29
1.4
0
31
1.55
2
33
1.7
LSBs
LSBs
V
PP
ADC_DN
ADC Input Dynamic Range (output
from 0 to 255)
ADC Clock Frequency
Output Pipeline Delay (3)
f
CLK
t
PCLK
12
MHz
CLK
cycles
ns
V
V
%
3
3
t
DADC
R
LADD
V
TOP
V
BOT
ADC_lin
Clock to Data Out (4)
Ladder Resistance
Top Reference Voltage
Bottom Reference Voltage
ADC Linearity
CLK positive edge, C
LOAD
= 20pF
Between Pins 36 and 37
Pin 36
Pin 37
Data out, input signal between
[V
BOT
+ 25mV ; V
TOP
- 25mV]
17
330
3.35
1.8
3.2
1.71
3.5
1.89
1
Notes :
3. The signal is being sampled as long as ADC_CLK is high.
4. See Figure 6 for data reading timing constraint.
0
Sampling
Period
Pixel N
Data available
on falling edge of clock
t
DADC
Pixel N-4
Pixel N-3
Pixel N-2
Pixel N-1
Pixel N
ADC_IN
ADC_CLOCK
DATA_OUT
Pixel N+1
0
Figure 6
Due to t
DADC
, and to make sure the data are read when they are stable, please read the data on the falling
edge of the ADC clock.
STV0502
9/15
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