參數(shù)資料
型號: STSR30D
廠商: 意法半導(dǎo)體
英文描述: SYNCHRONOUS RECTIFIER SMART DRIVER FOR FLYBACK
中文描述: 智能驅(qū)動同步整流用于回掃
文件頁數(shù): 3/10頁
文件大?。?/td> 197K
代理商: STSR30D
STSR30
3/10
PIN DESCRIPTION
Pin N°
Symbol
Name and Function
1
INHIBIT
This input enables OUT
GATE
to work when its voltage is lower than the negative
threshold voltage (V
INHIBIT
<V
H
). If V
INHIBIT
>V
H
the OUT
GATE
will be high for a
minimum conduction time (t
ON(GATE)
). In typical flyback converter application, it is
possible to turn off the synchronous MOSFET when the current through it tends to
reverse, allowing discontinuous conduction mode and providing protection to the
converter from eventual sinking current from the load.
A blanking time of 700ns allows operation when some voltage ringing is present
during turn-off of primary switch.
Absolute maximum voltage rating of the pin can be exceeded limiting the current
flowing into the pin to 10mA max.
Gate Drive signal for Synchronous MOSFET. Anticipation [t
ANT
] in turning off
OUT
GATE
is provided when the clock input goes to low level.
Reference for all the control logic signals. This pin is completely separated from
the PWRGND to prevent eventual disturbances to affect the control logic.
Reference for power signals, this pin carries the full peak currents for the output.
The supply voltage range from 4.5V to 5.5V allows applications with logic gate
threshold mosfets. UVLO feature guarantees proper start-up while it avoids
undesirable driving during eventual dropping of the supply voltage.
This pin allows turning off the device completely when kept to low level. In this
condition the IC power consumption is strongly reduced. When this pin goes to
high value, OUT
GATE
turns to switching again according to the CK signal.
The voltage on this pin sets the anticipation in turning off the OUTGATE. It is
possible to choose among three different anticipation times by discrete
partitioning of the supply voltage [ANT].
This input provides synchronization for IC’s operations, being the transitions
between the two output conditions based on a positive threshold, equal for the
two slopes. A smart internal control logic mechanism using a 15MHz internal
oscillator generates proper anticipation timing at the turn-off of each output. This
feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual
shoot-through situation on secondary side at both transitions. Clock revelation
mechanism makes the operation of STSR30 particularly suitable for flyback
adaptors application allowing correct operation during discontinuous mode.
Absolute maximum positive voltage rating of the pin can be exceeded limiting the
current flowing into the pin to 10mA max.
2
OUT
GATE
3
SGLGND
4
5
PWRGND
V
CC
6
DISABLE
7
SETANT
8
CK
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