參數(shù)資料
型號(hào)： STR712FR2T6
廠商： 意法半導(dǎo)體
英文描述： ARM7TDMI? 16/32-BIT MCU WITH FLASH, USB, CAN 5 TIMERS, ADC, 10 COMMUNICATIONS INTERFACES
中文描述： ARM7TDMI的？ 16/32位微控制器5定時(shí)器，ADC和10 COMMUNICAT離子接口與閃存，USB，可以
文件頁(yè)數(shù)： 36/49頁(yè)
文件大小： 678K
代理商： STR712FR2T6
STR71xF - ELECTRICAL CHARACTERISTICS
36/49
Table 18. PLL2 Electrical Characteristics
f
FREE1
PLL free running frequency
FREF_RANGE = 0
MX[1:0]=’01’ or ‘11’
FREF_RANGE = 0
MX[1:0]=’00’ or ‘10’
FREF_RANGE = 1
MX[1:0]=’01’ or ‘11’
FREF_RANGE = 1
MX[1:0]=’00’ or ‘10’
FREF_RANGE = 0
Stable Input Clock
Stable V
33IOPLL
, V
18
FREF_RANGE = 1
Stable Input Clock
Stable V
33IOPLL
, V
18
t
PLL
= 4 MHz, MX[1:0]=’11’
Global Output division = 32
(Output Clock = 2 MHz)
1
MHz
2
MHz
2
MHz
4
MHz
t
LOCK1
PLL lock time
300
μ
s
600
μ
s
t
JITTER1
PLL jitter (peak to peak)
0.7
2
ns
Symbol
Parameter
Test Conditions
Value
Typ
Unit
Min
Max
140
3.0
5
f
PLLCLK2
PLL output clock
f
PLL
x 28
FREF_RANGE = 0
FREF_RANGE = 1
FREF_RANGE = 0
Stable Input Clock
Stable V
33IOPLL
, V
18
FREF_RANGE = 1
Stable Input Clock
Stable V
33IOPLL
, V
18
t
PLL
= 4 MHz, MX[1:0]=’11’
Global Output division = 32
(Output Clock = 2 MHz)
MHz
MHz
MHz
f
PLL2
PLL input clock
1.5
3.0
t
LOCK2
PLL lock time
300
μ
s
600
μ
s
t
JITTER2
PLL jitter (peak to peak)
0.7
2
ns
Symbol
Parameter
Test Conditions
Value
Typ
Unit
Min
Max
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