參數(shù)資料
型號(hào)： STP1100BGA-100
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, PBGA272
封裝： PLASTIC, BGA-272
文件頁(yè)數(shù)： 27/32頁(yè)
文件大小： 168K
代理商： STP1100BGA-100
4
STP1100BGA
Preliminary
SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces
microSPARC-IIep
December 1997
Sun Microsystems, Inc
PCI Bus Interface
The PCI bus interface complies with the industry standard PCI Local Bus Specication version 2.1. It provides
a 32-bit 33MHz bus interface. Its features include endian conversion for different data byte ordering, PCI Host
and Satellite mode, a dedicated 16-entry translation lookaside buffer (TLB) dedicated for I/O transactions, a
PCI arbiter, and PCI clock, reset and interrupt handler. As a PCI Host, microSPARC-IIep performs PCI bus
arbitration, PCI clock, reset and interrupt handling. As a PCI Satellite, microSPARC-IIep relinquishes the PCI
Host functionalities to the external PCI Host.
Other features supported by the PCI Bus interface include:
Programmed input/output (PIO) transactions between the microSPARC-IIep and external PCI devices.
PCI Host or Satellite mode selected by input pins during power-up.
Programmable conguration of external PCI devices (Type 0 and Type 1) while under PCI Host mode.
Programmable conguration by external PCI Host while under PCI Satellite mode.
Buffers with matching ll and drain rate allow extended burst transfers.
Direct transactions between PCI masters and PCI slaves.
Two PCI bus fairness access arbitration protocols: same-level round robin and three-level round robin.
Direct virtual memory access (DVMA) transactions between PCI masters and the microSPARC-IIep slave
memory interface (referred to as PCI DVMA) using the software-controlled IOTLB to generate physical
DRAM addresses.
Booting from the PCI Bus from address selected by user.
While under standby mode to reduce power consumption, the PCI interface consumes minimal power to
support clock generation and wake-up when interrupted.
Two 32-bit timers or one 32-bit timer and one 64-bit counter available.
Interrupt handler supports up to eight programmable interrupt input/output lines.
Flash Memory Interface
Using an industry-standard programming algorithm, the microSPARC-IIep ash memory interface is com-
patible with 28FxxxXX ash memory devices. The interface has a programmable latency to allow ash
memory access time of up to 45 processor clocks. After power-up, the default latency of the interface is 45 pro-
cessor clocks. It can then be programmed to have an access latency from 6 to 45 processor clocks in increments
of 3 processor clocks.
The ash memory interface supports up to 16MBytes of data. It supports both 32-bit and 8-bit data accesses as
selected by a boot-mode select input pin. microSPARC-IIep is pin-selectable to boot from the ash memory
interface or the PCI address space.
JTAG Test Bus Interface
The microSPARC-IIep provides a ve-wire test access port (TAP) interface to support boundary scan and
clock control. This interface is compatible with IEEE 1149.1 specication, IEEE Standard Test Access Port and
Boundary Scan Architecture. This allows efcient access to any single chip in a scan daisy-chain without
board-level multiplexing.
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