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參數(shù)資料
| 型號： | STM86312 |
| 廠商： | 意法半導體 |
| 英文描述： | 1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER |
| 中文描述： | 1 / 4轉到1/11-DUTY變頻控制器/驅動器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 434K |
| 代理商： | STM86312 |
STM86312
5/16
Table 6: Switching Characteristics
(V
DD
= 4.5 to 5.5V, V
SS
= 0V, V
EE
= V
DD
- 35V, T
A
= -20 to 70°C,
unless otherwise noted. Typical values are at T
A
= 25°C)
Table 7: Timing Characteristics
(V
DD
= 4.5 to 5.5V, T
A
= -20 to 70°C, unless otherwise noted. Typical
values are at T
A
= 25°C)
NOTE 1: Refer to page Serial Communication Format.
DISPLAY RAM ADDRESS AND DISPLAY MODE
The display RAM stores the data transmitted from an external device to the STM86312 through the serial
interface; addresses are as follows, in 8-bits unit:
"0" in memory means V
EE
on output; "1" in memory means V
DD
on output.
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
t
PLZ
t
PZL
t
TZH1
t
TZH2
Propagation Delay
CLK
→
D
OUT
R
L
= 10 k
, C
L
= 15 pF
300
100
2
0.5
ns
Rise Time
C
L
= 300 pF
Seg1 to Seg11
Grid1 to Grid6, Seg12/
Grid11 to Seg16/Grid7
μs
t
THZ
f
MAX
C
I
Fall Time
Maximum Clock Frequency
Input Capacitance
C
L
= 300 pF, Segn, Gridn
Duty = 50%
120
μs
MHz
pF
1
15
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
PW
CLK
PW
STB
t
SETUP
t
HOLD
t
CLK-STB
t
WAIT
Clock Pulse Width
Strobe Pulse Width
Data Setup Time
Data Hold Time
Clock-Strobe Time
Wait Time (Note 1)
400
1
100
100
1
1
ns
μs
ns
ns
μs
μs
CLK
↑→
STB
↑
CLK
↑→
CLK
↓
Seg1
Seg4
Seg8
Seg12
Seg16
00 H
L
02 H
L
04 H
L
06 H
L
08 H
L
0A H
L
0C H
L
0E H
L
10 H
L
12 H
L
14 H
L
00 H
U
02 H
U
04 H
U
06 H
U
08 H
U
0A H
U
0C H
U
0E H
U
10 H
U
12 H
U
14 H
U
01 H
L
03 H
L
05 H
L
07 H
L
09 H
L
0B H
L
0D H
L
0F H
L
11 H
L
13 H
L
15 H
L
01 H
U
03 H
U
05 H
U
07 H
U
09 H
U
0B H
U
0D H
U
0F H
U
11 H
U
13 H
U
15 H
U
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
DIG10
DIG11
b0
b3 b4
b7
XX H
L
XX H
U
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相關代理商/技術參數(shù) |
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