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STM1810/1811/1812/1813/1815/1816/1817/1818
OPERATION
Reset Output
The STM181x asserts a reset signal to the Micro-
controller (MCU) whenever V
CC
goes below the
reset threshold (V
RST
), and is guaranteed valid
down to V
CC
= 1.0V (0° to 105°C). A microcontrol-
ler’s (MCU) reset input starts the MCU in a known
state. The STM1810 - STM1813/ STM1815 -
STM1818 Low Power Reset circuits assert reset to
prevent code-execution errors during power-up,
power-down, and brownout conditions (
Figure
8., page 7
).
During power-up, once V
CC
exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, t
rec
. After this interval, RST
returns high.
If V
CC
drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period. Any time V
CC
goes
below the reset threshold, the internal timer clears.
The reset timer starts when V
CC
returns above the
reset threshold. Reset t
rec
is also triggered by an
externally initiated rising edge on the RST pin
(STM1813/STM1818), following a low signal of
1.5μs minimum duration.
Push-Button Detect Reset (STM1813/1818)
Many systems require push-button reset capability
(
Figure 9., page 8
), allowing the user or external
logic circuitry to initiate reset. On the STM1813/
STM1818, a logic low on RST held for greater than
1.5μs asserts a reset. RST deasserts following a
100ms minimum reset time-out delay (t
rec
). A
manual reset input shorter than 1.5μs may release
RST without the 100ms minimum reset time-out
delay. To facilitate use with mechanical switches,
the STM1813/STM1818 contain internal de-
bounce circuitry. A debounced waveform is shown
in
Figure 10., page 8
The RST output has an inter-
nal 5.5k
pull-up resistor.
Interfacing to Bidirectional Microcontrollers
(MCU’s)
As the RST output on the STM1811/STM1816 is
open drain, these devices interface easily with
MCU’s that have bidirectional reset pins. Connect-
ing the μP supervisor’s reset (RST) output directly
to the microcontroller’s reset (RST) pin allows ei-
ther device to assert reset (
Figure 11., page 8
). No
external pull-up resistor is required, as it is within
the STM1811/STM1816.
Negative Going V
CC
Transients
The STM181x are relatively immune to negative-
going
V
CC
transients
20., page 13
shows typical transient duration ver-
sus reset comparator overdrive (for which the
STM181x will NOT generate a reset pulse). The
graph was generated using a negative pulse ap-
plied to V
CC,
starting at 0.5V above the actual re-
set threshold and ending below it by the
magnitude indicated (comparator overdrive). The
graph indicates the maximum pulse width a nega-
tive V
CC
transient can have without causing a re-
set pulse. As the magnitude of the transient
increases (further below the threshold), the maxi-
mum allowable pulse width decreases. Any com-
bination of duration and overdrive which lies under
the curve will NOT generate a reset signal. Typi-
cally, a V
CC
transient that goes 100mV below the
reset threshold and lasts 20μs or less will not
cause a reset pulse. A 0.1μF bypass capacitor
mounted as close as possible to the V
CC
pin pro-
vides additional transient immunity.
Valid RST Output Down to V
CC
= 0V
When V
CC
falls below 1V, the RST output no long-
er sinks current, but becomes an open circuit. In
most systems this is not a problem, as most MCUs
do not operate below 1V. However, in applications
where RST output must be valid down to 0V, a
pull-down resistor may be added to hold the RST
output low (see
Figure 12., page 9
). This resistor
must be large enough to not load the RST output,
and still be small enough to pull the output to
ground. A 100k
resistor is recommended.
Note:
The same situation applies for the active-
high RST of the STM1810/1812. A 100k
pull-up
resistor to V
CC
should be used if RST must remain
valid for V
CC
< 1.0V.
(glitches).
Figure
Figure 8. Reset Timing Diagram
Note: 1. RST for STM1812 and STM1817
AI09653
RST
RST
(1)
VCC
VRST
VCC (min)
trec
trec