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參數(shù)資料
| 型號(hào)： | STK3NA50 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR |
| 中文描述： | ? -快速通道增強(qiáng)型功率MOS器件 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 180K |
| 代理商： | STK3NA50 |
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
t
r
Turn-on Time
Rise Time
V
DD
= 250 V
R
G
= 18
(see test circuit, figure 3)
V
DD
= 400 V
R
G
= 18
(see test circuit, figure 5)
V
DD
= 400 V
I
D
= 1.5 A
V
GS
= 10 V
14
23
20
30
ns
ns
(di/dt)
on
Turn-on Current Slope
I
D
= 3 A
V
GS
= 10 V
340
A/
μ
s
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
I
D
= 3 A
V
GS
= 10 V
21
6
9
28
nC
nC
nC
SWITCHING OFF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 400 V
R
G
= 18
(see test circuit, figure 5)
I
D
= 3 A
V
GS
= 10 V
13
11
26
18
16
35
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(
)
Source-drain Current
Source-drain Current
(pulsed)
Forward On Voltage
2.7
10.8
A
A
V
SD
(
)
t
rr
I
SD
= 2.7 A
V
GS
= 0
di/dt = 100 A/
μ
s
T
j
= 150
o
C
1.6
V
Q
rr
I
RRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I
SD
= 3 A
V
DD
= 100 V
(see test circuit, figure 5)
350
4.2
24
ns
μ
C
A
(
) Pulsed: Pulse duration = 300
μ
s, duty cycle 1.5%
(
) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
STK3NA50
3/10
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