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參數(shù)資料
| 型號： | STEL-1377Q |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP63 |
| 封裝： | 3.750 X 1.600 INCH, 0.40 INCH HEIGHT, DIP-63 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 231K |
| 代理商： | STEL-1377Q |
7
STEL-1377Q/S
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the
device. Exposure of the device to these conditions for extended periods may also affect device
reliability.
Symbol
Parameter
Range
Units
Tstg
Storage Temperature
–65 to +150
°C
Ta
Operating Temperature
–40 to +85
°C
VDDmax
Max. voltage between VCC and VSS
+7 to –0.7
volts
VEEmax
Max. voltage between VEE and VSS
–7 to +0.7
volts
VI/O(max)
Max. voltage on any input pin
VDD+0.7
volts
VI/O(min)
Min. voltage on any input pin
VSS–0.7
volts
RECOMMENDED OPERATING CONDITIONS (The VSS pins should be connected to ground)
Symbol
Parameter
Range
Units
VDD
Supply Voltage, +5 volts
+5
± 10%
volts
VEE
Supply Voltage, –5.2 volts
–5.2
± 10%
volts
Ta
Operating Temperature (Ambient)
0 to +70
°C
D.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = –5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IDD
Supply Current, +5 volts
700
mA
@ 60 MHz clock (/Q)
IEE
Supply Current, –5.2 volts
950
mA
@ 60 MHz clock (/Q)
VIH(min)
Min. High Level Input Voltage
2.0
volts
Guaranteed Logic '1'
VIL(max)
Max. Low Level Input Voltage
0.8
volts
Guaranteed Logic '0'
IIH(max)
Max. High Level Input Current
10
AV
IN = +5.0 volts
IIL(max)
Max. Low Level Input Current
–10
AV
IN = 0 volts
VCLK
Clock Input Voltage
0.4
1.0
volts
peak to peak
OUTPUT CHARACTERISTICS
Symbol
Parameter
Min. Typ. Max. Units
Conditions
PO(max)
Max. Output Power
–5
dBm
TCFS
Full-scale output Temp. coefficient
0.06
0.12
%
50
load
GE
Output glitch energy
15
pV.sec.
Err(i)
Output integral linearity
–0.1
+0.1
%
of full-scale output
VSPUR
Spurious signal level
–65
dBc fOUT < .25 x fCLK
VSPUR
Spurious signal level
–62
dBc
.25 x fCLK < fOUT < .33 x fCLK
VSPUR
Spurious signal level
–60
dBc
.33 x fCLK < fOUT < .45 x fCLK
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