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參數(shù)資料
| 型號(hào)： | STA003 |
| 英文描述： | MPEG 2.5 LAYER III AUDIO DECODER |
| 中文描述： | 2.5第三層的MPEG音頻解碼器 |
| 文件頁(yè)數(shù)： | 6/32頁(yè) |
| 文件大小： | 299K |
| 代理商： | STA003 |
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SCLK_POL=0
SCLK_POL=2
SCKR
SCKR
SDI
BIT_EN
D98AU968
DATA IGNORED
Figure 5.
Serial Input Interface Clocks
CHANNEL
DECODER
μ
P
MPEG
DECODER
IIC
D97AU665A
IIC
SDO
SCKT
LRCKT
SERIAL AUDIO INTERFACE
SDI
SCKR
BIT_EN
XTO
MASTER CLK
DAC
RX
TX
XTI
FILT
PLL
OCLK
SCL
SDA
SRC-INT
Figure 4.
MPEG Decoder Interfaces.
2.2 - Serial Input Interface
STA003T receives the input data thought the Se-
rial Input Interface (Fig.4). It is a serial communi-
cation interface connected to the SDI (Serial Data
Input) and SCKR (Receiver Serial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock.The BIT_EN pin, when set to low,
forces the bitstream input interface to ignore the
incoming data. The possible configurations are
described in Fig. 5.
The bitstream must be sent MSB first to
STA003T.
2.3 - PLL & Clocks Generation System
The STA003T has a clock generation system that
is used by the device core to adjust the core
speed, for power saving, adapting the processing
speed to the needs of the decoded audio pro-
gram. The clocks generation system is even used
to generate all the PCM output interface clocks:
SCKT, LRCKT, and OCLK.
The block diagram in Fig. 6 is a description of
STA003T clocks generation system. The input of
STA003T clocks system is a 14.72MHz input
clock.
Internally it is composed by a PLL loop, and the
VCO output is fed into a divider stage, used to
program the Core speed and the PCM interface
clocks. Several registers are programmed by the
Layer III decoder core, and by the user, when a
specific interface configuration is required.
The PLL can be programmed by a set of regis-
ters, as described in the I2C Registers section,
The particularity of the STA003T clocks genera-
tion system is the possibility to modify the Audio
Sampling Frequency (LRCKT) in steps of few
ppm to compensate dynamically the audio sam-
pling rate offset between the receiver and the
broadcasting station.
The compensation is done by the STA003T core
without requiring interaction with the application
controller and the sampling rate compensation
produces a jittering effect outside the audible
range.
The device implements a sampling rate offset
control receiving by STA002 (WorldSpace Chan-
nel Decoder) a dedicated signal every decoded
Broadcast Channel Frame (432ms).
STA003T
6/32
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