
POWER-ON DATA PROTECTION
In orderto prevent datacorruption and inadvertent
write operations during power up, a Power On
Reset(POR)circuit resetsallinternalprogramming
circuitry and sets the device in the Write Disable
mode. When V
CC
reaches its functionalvalue, the
deviceisproperlyreset (in the Write Disablemode)
and is ready to decode and execute an incoming
instruction. A stable V
CC
must be applied before
any logic signal.
INSTRUCTIONS
The ST93CS66/67 has eleven instructions, as
shown in Table 6. Each instructionis composedof
a 2 bitop-code andan 8bit address. Eachinstruc-
tion is preceded by the rising edge of the signal
appliedonthe Chip Select(S) input(assumingthat
the Clock C is low). The data input D is then
sampled upon the following rising edges of the
clock C until a ’1’ is sampled and decoded by the
ST93CS66/67as a Start bit.
The ST93CS66/67 is fabricated inCMOS technol-
ogyandisthereforeableto run from zeroHz (static
inputsignals)up to themaximumratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). Whena READinstruction
is received, the instruction and address are de-
codedand thedata from thememory is transferred
intoanoutputshiftregister.Adummy’0’bitisoutput
first followedby the 16 bitword with the MSBfirst.
Instruction
Description
W
pin
(1)
PRE
pin
Op
Code
Address
(1)
Data
Additional
Information
READ
Read Data from Memory
X
’0’
10
A7-A0
Q15-Q0
WRITE
Write Data to Memory
’1’
’0’
01
A7-A0
D15-D0
Write is executed if
the address is not
inside the
Protected area
PAWRITE
Page Write to Memory
’1’
’0’
11
A7-A0
D15-D0
Write is executed if
all the addresses
are not inside the
Protected area
WRALL
Write All Memory
’1’
’0’
00
01XX XXXX
D15-D0
Write all data ifthe
Protect Register is
cleared
WEN
Write Enable
’1’
’0’
00
11XX XXXX
WDS
Write Disable
X
’0’
00
00XX XXXX
PRREAD
Protect RegisterRead
X
’1’
10
XXXX XXXX
Q8-Q0
Data Output =
Protect Register
content + Protect
Flag bit
PRWRITE
Protect Register Write
’1’
’1’
01
A7-A0
Data above
specified address
A7-A0 are
protected
PRCLEAR
Protect Register Clear
’1’
’1’
11
1111 1111
Protect Flag is also
cleared (cleared
Flag = 1)
PREN
Protect Register Enable
’1’
’1’
00
11XX XXXX
PRDS
Protect Register Disable
’1’
’1’
00
0000 0000
OTPbit is set
permanently
Note:
1. X = don’t care bit.
Table 6. InstructionSet
6/16
ST93CS66, ST93CS67