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參數(shù)資料
| 型號： | ST93CS66 |
| 廠商： | 意法半導體 |
| 英文描述： | 4K (256 x 16) Serial Microwire EEPROM(4K位串行EEPROM) |
| 中文描述： | 4K的（256 × 16）系列微型導線的EEPROM（4K的位串行EEPROM的） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 124K |
| 代理商： | ST93CS66 |
Output data changes are triggered by the Low to
High transitionof the Clock(C).The ST93CS66/67
will automatically increment the address and will
clockout the next wordas long as the Chip Select
input (S) is heldHigh. In thiscasethedummy ’0’ bit
is NOT output between words and a continuous
streamof data can be read.
Write Enable and Write Disable
The Write Enableinstruction(WEN) authorizesthe
following Write instructions to be executed, the
Write Disable instruction (WDS) disables the exe-
cution of the following Erase/Write instructions.
When power is first applied, the ST93CS66/67
enters the Disable mode. When the Write Enable
instruction (WEN) is executed, Write instructions
remain enabled until a Write Disable instruction
(WDS) is executed or if the Power-on reset circuit
becomes active due to a reduced V
CC
. To protect
the memory contentsfrom accidentalcorruption,it
is advisable to issue the WDS instruction after
everywrite cycle.
The READ instruction is not affected by the WEN
or WDSinstructions.
Write
The Write instruction (WRITE) is followed by the
address and the word to be written. The Write
Enable signal (W) must be held high during the
WRITE instruction.Data inputD is sampled on the
Low to High transition of the clock. After the last
data bit has been sampled, Chip Select (S) must
be brought Low before the next rising edge of the
clock(C), inorder to startthe self-timed program-
mingcycle,providing thattheaddressisNOTinthe
protected area. If the ST93CS66/67 is still per-
forming the programmingcycle,theBusy signal (Q
= 0) will be returnedif the Chip Select input (S) is
driven high, and the ST93CS66/67will ignore any
dataonthebus.Whenthewritecycle iscompleted,
the Ready signal (Q = 1) will indicate (if S is driven
high) that the ST93CS66/67 is ready to receive a
new instruction.
Page Write
APage Write instruction(PAWRITE) containsthe
firstaddress to be writtenfollowed by up to 4data
words. The Write Enable signal (W) must be held
High duringtheWriteinstruction.Inputaddressand
data are read on the Low to High transition of the
clock. After the receipt of each data word, bits
A1-A0 of the internal address register are incre-
mented, the high order bits A7-A2 remaining un-
changed. Users must take care by software to
ensurethat the last wordaddresshasthe samesix
upper order address bits as the initial address
transmitted to avoid address roll-over.
After theLSBof the last data word, ChipSelect (S)
must be broughtLowbeforethenext risingedge of
the Clock (C). The falling edge of Chip Select (S)
initiates the internal, self-timed write cycle. The
Page Write operation will not be performed if any
of the 4 words is addressingthe protectedarea. If
the ST93CS66/67is still performing the program-
ming cycle, the Busysignal (Q = 0) will be returned
if the Chip Select input (S) is driven high, and the
ST93CS66/67 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93CS66/67isready toreceiveanewinstruc-
tion.
Write All
The WriteAll instruction(WRALL) isvalidonlyafter
the ProtectRegisterhas beenclearedbyexecuting
a PRCLEAR (Protect Register Clear) instruction.
The Write All instructionsimultaneouslywrites the
whole memory with the same data word included
in the instruction. The Write Enable signal (W)
must be held High before and during the Write
instruction.Input addressand dataare read on the
Low to High transition of the clock.
ST93CS66/67 is stillperforming the programming
cycle, the Busysignal(Q = 0)will be returnedif the
Chip Select input (S) is driven high, and the
ST93CS66/67 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93CS66/67isready toreceiveanewinstruc-
tion.
If the
MEMORYWRITEPROTECTION ANDPROTECT
REGISTER
The ST93CS66/67 offers a Protect Register con-
taining the bottom address of the memory area
which has to be protected against write instruc-
tions. In addition to this Protect Register, two flag
bitsareusedtoindicatetheProtectRegisterstatus:
the Protect Flag enabling/disablingthe protection
of theProtectRegisterandtheOTPbitwhich, when
set, disables access to the Protect Register and
thus preventsany further modificationsof this Pro-
tect Register value. The content of the Protect
Register is defined when using the PRWRITE in-
struction,it maybe read when using the PRREAD
instruction. A specific instruction PREN (Protect
Register Enable) allows the user to execute the
protect instructions PRCLEAR, PRWRITE and
PRDS; this PREN instruction beingused together
with the signals applied on the input pins PRE
(Protect Register Enable pin) and W (Write En-
able).
7/16
ST93CS66, ST93CS67
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST93CS66B1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| ST93CS66B1013TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4K 256 x 16 SERIAL MICROWIRE EEPROM |
| ST93CS66B3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| ST93CS66B3013TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4K 256 x 16 SERIAL MICROWIRE EEPROM |
| ST93CS66B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
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