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參數(shù)資料
| 型號(hào)： | ST92T141K4M6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 25 MHz, MICROCONTROLLER, PDSO34 |
| 封裝： | PLASTIC, SO-34 |
| 文件頁(yè)數(shù)： | 139/179頁(yè) |
| 文件大?。?/td> | 1905K |
| 代理商： | ST92T141K4M6 |
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ST92141 - EM CONFIGURATION REGISTERS (EM)
4 EM CONFIGURATION REGISTERS (EM)
In ST9 devices with external memory, the EM reg-
isters (External Memory Registers) are used to
configure the external memory interface. In the
ST92141, only the BSZ, ENCSR and DPREM bits
must be programmed. All other bits in these regis-
ters must be left at their reset values.
EM REGISTER 1 (EMR1)
R245 - Read/Write
Register Page: 21
Reset value: 1000 0000 (80h)
Bit 7:2 = Reserved.
Bit 1 = BSZ:
Buffer size.
0: I/O ports P3.6, P3.5, P5.0, P5.2 use output buff-
ers with standard current capability (less noisy).
1: I/O ports P3.6, P3.5, P5.0, P5.2 use output buff-
ers with high current capability (more noisy)
Bit 0 = Reserved.
EM REGISTER 2 (EMR2)
R246 - Read/Write
Register Page: 21
Reset value: 0000 1111 (0Fh)
Bit 7 = Reserved, keep in reset state.
Bit 6 = ENCSR:
Enable Code Segment Register.
This bit is set and cleared by software. It affects
the ST9 CPU behaviour whenever an interrupt re-
quest is issued.
0: The CPU works in original ST9 compatibility
mode. For the duration of the interrupt service
routine, ISR is used instead of CSR, and the in-
terrupt stack frame is identical to that of the orig-
inal ST9: only the PC and Flags are pushed.
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster in-
terrupt response time. The drawback is that it is
not possible for an interrupt service routine to
perform inter-segment calls or jumps: these in-
structions would update the CSR, which, in this
case, is not used (ISR is used instead). The
code segment size for all interrupt service rou-
tines is thus limited to 64K bytes.
1: ISR is only used to point to the interrupt vector
table and to initialize the CSR at the beginning
of the interrupt service routine: the old CSR is
pushed onto the stack together with the PC and
flags, and CSR is then loaded with the contents
of ISR. In this case, iret will also restore CSR
from the stack. This approach allows interrupt
service routines to access the entire 4 Mbytes of
address space; the drawback is that the inter-
rupt response time is slightly increased, be-
cause of the need to also save CSR on the
stack. Full compatibility with the original ST9 is
lost in this case, because the interrupt stack
frame is different; this difference, however,
should not affect the vast majority of programs.
Bit 5 = DPRREM:
Data Page Registers remapping
0: The locations of the four MMU (Memory Man-
agement Unit) Data Page Registers (DPR0,
DPR1, DPR2 and DPR3) are in page 21.
1: The four MMU Data Page Registers are
swapped with that of the Data Registers of ports
0-3.
Refer to Figure 11
Bit 4:0 = Reserved, keep in reset state.
70
1
000
0
BSZ
0
70
0
ENCSR DPREM
01111
1
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