參數(shù)資料
型號(hào)： ST92R195C9
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 24 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 159/208頁
文件大?。?/td> 2312K
代理商： ST92R195C9
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ST92R195C - EXTERNAL MEMORY INTERFACE (EXTMI)
4 EXTERNAL MEMORY INTERFACE (EXTMI)
4.1 INTRODUCTION
In the ST9+, memory accesses are basically 2
clock cycles long (in the ST9OLD they were 3
clock cycles long). Timing access constraints must
be carefully studied when building an application
with external memory.
In order to also handle slow external memories,
programmable Wait states (from 0 to 3) have been
added on Data Strobe (DSN) and Address Strobe
(AS). These wait states are in addition to the wait
states inserted on program memory and data
memory accesses already available on ST9 (see
also WCR register in the Reset and Clock Control
chapter).
Some memory bus options may be selected
through 2 registers (EMR1-EMR2) located in page
21 of the paged registers. Some interface signals
are also affected by WCR (R252 Page 0).
If the two registers EMR1 and EMR2 are set to the
proper values, the new ST9+ memory access cy-
cle is similar to that of the original ST9, with the
only exception that it is composed of just two sys-
tem clock phases, named T1 and T2.
During phase T1 the memory address is output on
the AS rising edge and is valid on the falling edge
of AS.
During phase T2, two forms of behaviour are pos-
sible. If the memory access is a Read cycle,
DAT[7:0] pins are released in high-impedance un-
til the next T1 phase and the data signals are sam-
pled by the ST9+ on the rising edge of DSN. If the
memory access is a Write cycle, on the falling
edge of DSN, DAT[7:0] outputs data to be written
in the external memory. Those data signals are
valid on the rising edge of DSN and are main-
tained stable until the next address is output. Note
that DSN is pulled low at the beginning of phase
T2 only during an external memory access.
The next paragraph describes the meaning and
the behaviour of the external memory signals and
the chapter after summarizes the meaning of the
bits of the two registers EMR1 and EMR2.
4.2 EXTERNAL MEMORY SIGNALS
Access to external memory is done using the fol-
lowing signals:
4.2.1 DSN
The Data Strobe (Output, Active low) is active dur-
ing the internal clock high-level phase of each T2
memory cycle. During an external memory read
cycle, the data on the DAT[7:0] bus must be valid
before the DSN rising edge. During an external
memory write cycle, the data on the DAT[7:0] bus
are output on the falling edge of DSN and they are
valid on the rising edge of DSN. When the internal
memory is accessed DSN is kept high during the
whole memory cycle. DSN is released in high-im-
pedance during a bus acknowledge cycle or under
processor control by setting the HIMP bit (MOD-
ER.0, R235). In Reset status, DSN is held high
with an internal weak pull-up.
The behaviour of this signal is affected by the fol-
lowing register bits:
– The MC bit in register EMR1 (R245.6, Page 15h)
If bit MC is reset, DSN keeps the ST9 meaning:
a rising edge of DSN indicates that data on DAT
port are valid to be written/read in/from the exter-
nal memory. When the internal memory is ac-
cessed, DSN is kept high during the whole
memory cycle.
If bit MC is set, DSN becomes OEN (Output EN-
able): it keeps the ST9 meaning during external
read operations but is forced to "1" during exter-
nal write operations.
– The DS2EN bit in register EMR1 (R245.5, Page
15h)
If bit DS2EN is reset, the behaviour of DSN
keeps the behaviour described in the previous
paragraph and depends on the value of the MC
bit.
If bit DS2EN is set, the behaviour of DSN de-
pends on which MMU segment area is pointed
to, based on the MMU5 bit value (if MMU5= 0,
DSN is forced to "1" during the whole memory cy-
cle; if MMU5= 1, DSN will act as described in the
previous paragraph).
Note: Setting DS2EN to "1" requires using of a
second generic control signal called "DS2N".
As DS2N is NOT IMPLEMENTED into the
ST92R195C, the DS2EN bit MUST ALWAYS
BE KEPT TO "0".
– Bit BSZ in register EMR1 (R245.1, Page 15h):
This bit forces the pin in High Impedance.
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