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參數(shù)資料
| 型號(hào)： | ST90E158P9L0 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CQCC84 |
| 封裝： | WINDOWED, CERAMIC, LCC-84 |
| 文件頁(yè)數(shù)： | 64/189頁(yè) |
| 文件大?。?/td> | 3326K |
| 代理商： | ST90E158P9L0 |
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SERIAL COMMUNICATIONS INTERFACE (SCI)
REGISTER DESCRIPTION (Cont’d)
INTERRUPT VECTOR REGISTER (S_IVR)
R244 - Read/Write
Reset value: undefined
Bit 7:3 = V[7:3]:
SCI Interrupt Vector Base Ad-
dress.
User programmable interrupt vector bits for trans-
mitter and receiver.
Bit 2:1 = EV[2:1]:
Encoded Interrupt Source.
Both bits EV2 and EV1 are read only and set by
hardware according to the interrupt source.
Bit 0 = D0: This bit is forced by hardware to 0.
ADDRESS/DATA COMPARE REGISTER (ACR)
R245 - Read/Write
Reset value: undefined
Bit 7:0 = AC[7:0]:
Address/Compare Character.
With either 9th bit address mode, address after
break mode, or character search, the received ad-
dress will be compared to the value stored in this
register. When a valid address matches this regis-
ter content, the Receiver Address Pending bit
(RXAP in the S_ISR register) is set. After the
RXAP bit is set in an addressed mode, all received
data words will be transferred to the Receiver Buff-
er Register.
INTERRUPT MASK REGISTER (IMR)
R246 - Read/Write
Reset value: 0xx00000
Bit 7 = BSN:
Buffer or shift register empty inter-
rupt.
This bit selects the source of the transmitter regis-
ter empty interrupt.
0: Select a Shift Register Empty as source of a
Transmitter Register Empty interrupt.
1: Select a Buffer Register Empty as source of a
Transmitter Register Empty interrupt.
Bit 6 = RXEOB:
Received End of Block.
This bit is set by hardware only and must be reset
by software. RXEOB is set after a receiver DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a received block of data.
Bit 5 = TXEOB:
Transmitter End of Block.
This bit is set by hardware only and must be reset
by software. TXEOB is set after a transmitter DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a transmitted block of data.
Bit 4 = RXE:
Receiver Error Mask.
0: Disable Receiver error interrupts (OE, PE, and
FE pending bits in the S_ISR register).
1: Enable Receiver error interrupts.
Bit 3 = RXA:
Receiver Address Mask.
0: Disable Receiver Address interrupt (RXAP
pending bit in the S_ISR register).
1: Enable Receiver Address interrupt.
70
V7
V6
V5
V4
V3
EV2
EV1
0
EV2 EV1
Interrupt source
0
Receiver Error (Overrun, Framing, Parity)
0
1
Break Detect or Address Match
10
Received Data Pending/Receiver DMA
End of Block
11
Transmitter buffer or shift register empty
transmitter DMA End of Block
70
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
70
BSN
RXEOB TXEOB
RXE
RXA
RXB
RXDI
TXDI
9
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