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參數(shù)資料
| 型號(hào)： | ST90E158LV |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| 中文描述： | 微控制器16位產(chǎn)品的家庭多達(dá)64K的ROM /檢察官/ EPROM和2K的內(nèi)存 |
| 文件頁(yè)數(shù)： | 163/190頁(yè) |
| 文件大小： | 1152K |
| 代理商： | ST90E158LV |
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI)
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
CLOCK CONFIGURATION REGISTER (CCR)
R251 - Read/Write
Reset value: 0000 0000 (00h)
Bit 7 =
XTCLK
This bit, together with the OCLK bit, selects the
source for the transmitter clock. The following ta-
ble shows the coding of XTCLK and OCLK.
Bit 6 =
OCLK
This bit, together with the XTCLK bit, selects the
source for the transmitter clock. The following ta-
ble shows the coding of XTCLK and OCLK.
Bit 5 =
XRX
: External Receiver Clock Source
0: External receiver clock source not used.
1: Select the external receiver clock source.
Note:
The external receiver clock frequency must
be 16times thedata rate, or equal to the data rate,
depending on the status of the CD bit.
Bit 4 =
XBRG
: Baud Rate Generator Clock
Source
0: Select INTCLK for the baud rate generator.
1: Select the external receiver clock for the baud
rate generator.
Bit 3 =
CD
: Clock Divisor
The status of CD willdetermine the SCI configura-
tion (synchronous/asynchronous).
0: Select 16X clock mode for both receiver and
transmitter.
1: Select 1X clock mode for both receiver and
transmitter.
Note:
In 1X clock mode, the transmitter will trans-
mit data at one data bit per clock period. In 16X
mode each data bit period will be 16 clock periods
long.
Bit 2 =
AEN
: Auto Echo Enable
0: No auto echo mode.
1: Put the SCI in auto echo mode.
Note:
Auto Echo mode has the following effect:
the SCI transmitter is disconnected from the data-
out pin SOUT, which is driven directly by the re-
ceiver data-in pin, SIN. The receiver remains con-
nected to SIN and is operational, unless loopback
mode is also selected.
Bit 1 =
LBEN
: Loopback Enable
0: No loopback mode.
1: Put the SCI in loopback mode.
Note:
In this mode, the transmitter output is set to
a high level, the receiver input is disconnected,
and the output of the Transmitter Shift Register is
looped back into the Receiver Shift Register input.
All interrupt sources (transmitter and receiver) are
operational.
Bit 0 =
STPEN
: Stick Parity Enable.
0: The transmitter and the receiver will follow the
parity of even parity bit EP inthe CHCRregister.
1: The transmitter and the receiver will use the op-
posite parity type selected by the even parity bit
EP in the CHCR register.
7
0
XTCLK
OCLK
XRX
XBRG
CD
AEN
LBEN
STPEN
XTCLK
0
0
OCLK
0
1
Pin Function
Pin is used as a general I/O
Pin = TXCLK (used as an input)
Pin = CLKOUT (outputs theBaud
Rate Generator clock)
Pin =CLKOUT (outputs the Serial
expansion and synchronous
mode clock)
1
0
1
1
EP
SPEN
Parity (Transmitter &
Receiver)
Odd
Even
Even
Odd
0 (odd)
1 (even)
0 (odd)
1 (even)
0
0
1
1
9
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