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參數(shù)資料
| 型號(hào)： | ST90135 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| 中文描述： | 微控制器16位產(chǎn)品的家庭多達(dá)64K的ROM /OTP/ EPROM和2K的內(nèi)存 |
| 文件頁(yè)數(shù)： | 147/190頁(yè) |
| 文件大?。?/td> | 1152K |
| 代理商： | ST90135 |
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI)
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
9.5.4.1 Data transfer
Data to be transmitted by the SCI is firstloaded by
the program into the Transmitter Buffer Register.
The SCI will transfer the data into the Transmitter
Shift Register when the Shift Register becomes
available (empty). The Transmitter Shift Register
converts the parallel data into serial format for
transmission via the SCI Alternate Function out-
put, SerialData Out. On completion of thetransfer,
the transmitter buffer register interrupt pending bit
will be updated. If the selected word length is less
than 8 bits, the unused most significant bitsdo not
need to be defined.
Incoming serial data fromthe Serial Data Input pin
is converted into parallel format by the Receiver
Shift Register. At the end of the input data frame,
the validdata portion ofthe received word is trans-
ferred fromtheReceiver ShiftRegister intothe Re-
ceiver Buffer Register. All Receiver interrupt con-
ditions are updated at the time of transfer. If the
selected character format is less than 8 bits, the
unused most significant bits will be set.
The Frame Control and Status block creates and
checks the character configuration (Data length
and number of Stop bits), as well as the source of
the transmitter/receiver clock.
The internal Baud Rate Generator contains a pro-
grammable divide by “N” counter which can be
used to generate the clocks for the transmitter
and/or receiver. The baud rate generator can use
INTCLK or the Receiver clock input via RXCLK.
The Address bit/D9 is optional and may be added
to any word in Asynchronous and Serial Expan-
sion modes.It is commonly used innetwork or ma-
chine controlapplications. When enabled (AB set),
an address or ninth data bit can be added to a
transmitted word by setting the Set Address bit
(SA). This is then appended to the next word en-
tered into the (empty) Transmitter Buffer Register
and then cleared by hardware. On character input,
a set Address Bit can indicate that the data pre-
ceding the bit is an address which may be com-
pared in hardware with the value in the Address
Compare Register (ACR) to generate an Address
Match interrupt when equal.
The Address bit and Address Comparison Regis-
ter can also be combined to generate fourdifferent
types of Address Interrupt to suit different proto-
cols, based on the status of the Address Mode En-
able bit (AMEN) and the Address Mode bit (AM) in
the CHCR register.
The character match Address Interrupt mode may
be used as a powerful character search mode,
generating an interrupt on reception of a predeter-
mined character e.g. Carriage Return or End of
Block codes (Character Match Interrupt). This is
the only Address Interrupt Mode available in Syn-
chronous mode.
The LineBreakcondition is fully supported for both
transmission and reception. Line Break is sent by
setting the SB bit (IDPR). This causes the trans-
mitter output to be held low (after all buffered data
has been transmitted) for a minimum of one com-
plete word length and until the SB bit is Reset.
Break cannot be inserted into the transmitted
frame for the Synchronous mode.
Testing of the communications channel may be
performed using the built-in facilities of the SCI pe-
ripheral. Auto-Echo mode and Loop-Back mode
may be used individually ortogether. In Asynchro-
nous, Asynchronous with Synchronous Clock and
Serial Expansion modes they are available only on
SIN/SOUT pins through the programming of AEN/
LBEN bits in CCR. In Synchronous mode (SMEN
set) the above configurations are available on SIN/
SOUT, RXCLK/CLKOUT and DCD/RTS pins by
programming the AEN/LBEN bits and independ-
ently of the programmed polarity. In the Synchro-
nous mode case, when AEN is set, the transmitter
outputs (data, clock and control) are disconnected
from the I/O pins, which are driven directly by the
receiver input pins (Auto-Echo mode: SOUT=SIN,
CLKOUT=RXCLK and RTS=DCD, even if theyact
on the internal receiver with the programmed po-
larity/edge). WhenLBEN isset, thereceiver inputs
(data, clock and controls) are disconnected and
the transmitter outputs are looped-back into the re-
ceiver section (Loop-Back mode: SIN=SOUT, RX-
CLK=CLKOUT, DCD=RTS. The output pins are
locked to their programmed stand-by level and the
status of the INPL, XCKPL, DCDPL, OUTPL,
OCKPL and RTSPL bits inthe SICR register are ir-
relevant). Refer to Figure 80, Figure 81, and Fig-
ure 82 for these different configurations.
Table 27. Address Interrupt Modes
(1)
Not available in Synchronous mode
If 9th Data Bit is set
(1)
If Character Match
If Character Match and 9th Data Bit is set
(1)
If Character Match Immediately Follows BREAK
(1)
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST90135M4Q6 | 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90135M5Q6 | 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90135M6Q6 | 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90135M6T6 | 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90158 | 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST90135M4Q6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90135M4T6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST90135M5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY |
| ST90135M5LVT6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY |
| ST90135M5Q6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
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