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參數(shù)資料
| 型號： | ST7LNB1Y0M6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 536K |
| 代理商： | ST7LNB1Y0M6 |
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ST7LNB1Y0
Electrical characteristics
5.7
Control pin characteristics
5.7.1
Asynchronous RESET pin
Table 31.
Asynchronous RESET pin characteristics(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
0.3VDD
V
VIH
Input high level voltage
0.7VDD
Vhys
Schmitt trigger voltage hysteresis(4)
1V
VOL
Output low level voltage(5)
VDD=5 V
IIO=+5mA
0.5
1.0
V
IIO=+2mA
0.2
0.4
RON
Pull-up equivalent resistor(4)(6)
VDD=5V
20
40
80
k
tw(RSTL)out
Generated reset pulse duration
Internal reset sources
30
s
th(RSTL)in
External reset pulse hold time(7)
20
s
tg(RSTL)in
Filtered glitch duration(8)
200
ns
1.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can
be damaged when the ST7 generates an internal reset (LVD or watchdog).
2.
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the
VIL max. level specified in Section 5.7.1 on page 31. Otherwise the reset will not be taken into account internally.
3.
Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that
the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified
4.
Data based on characterization results, not tested in production.
5.
The IIO current sunk must always respect the absolute maximum rating specified in Table 19 and the sum of IIO (I/O ports
and control pins) must not exceed IVSS.
6.
The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltage on RESET pin between VILmax
and VDD.
7.
To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
8.
The reset network protects the device against parasitic resets.
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