參數(shù)資料
型號: ST7FLITE15F1B6
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI
中文描述: 8位單電壓閃存存儲器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,4定時器,微控制器的SPI
文件頁數(shù): 70/131頁
文件大小: 2046K
代理商: ST7FLITE15F1B6
ST7LITE1
70/131
1
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
11.4.2 Main Features
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
CPU
/4 max.)
f
CPU
/2 max. slave mode frequency (see note)
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
Note:
In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
11.4.3 General Description
Figure 41
shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master
Device
.
Figure 41. Serial Peripheral Interface Block Diagram
SPIDR
Read Buffer
8-Bit Shift Register
Write
Read
Data/Address Bus
SPI
STATE
SPIE
SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SERIAL CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
SPICR
SPICSR
Interrupt
request
MASTER
CONTROL
SPR2
0
7
0
7
SPIF WCOL
MODF
0
OVR
SSI
SSM
SOD
SOD
bit
SS
1
0
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