參數(shù)資料
型號: ST7FLITE15F1B6
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI
中文描述: 8位單電壓閃存存儲器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,4定時器,微控制器的SPI
文件頁數(shù): 51/131頁
文件大?。?/td> 2046K
代理商: ST7FLITE15F1B6
ST7LITE1
51/131
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
11.1.2 Main Features
Programmable free-running downcounter (64
increments of 16000 CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit
reaches zero
Optional
(configurable by option byte)
Hardware Watchdog selectable by option byte
reset
on
HALT
instruction
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 16000 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30μs.
Figure 32. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER
f
CPU
T6
T0
CLOCK DIVIDER
÷
16000
WATCHDOG CONTROL REGISTER (CR)
T1
T2
T3
T4
T5
1
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