參數(shù)資料
型號： ST7FLITE10F1M6
廠商： 意法半導體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI
中文描述： 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉換器，4定時器，微控制器的SPI
文件頁數(shù)： 83/131頁
文件大?。?/td> 2046K
代理商： ST7FLITE10F1M6
ST7LITE1
83/131
10-BIT A/D CONVERTER (ADC)
(Cont’d)
11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 =
EOC
End of
Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 =
SPEED
ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Bit 5 =
ADON
A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bit 4:3 =
Reserved.
Must be kept cleared.
Bit 2:0 =
CH[2:0]
Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
Bit 7:0 =
D[9:2]
MSB of
Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
Read/Write
Reset Value: 0000 00xx (0xh)
Bit 7:5 = Reserved. Forced by hardware to 0.
Bit 4 =
AMPCAL
Amplifier Calibration Bit
This bit is set and cleared by software. User is sug-
gested to use this bit to calibrate the ADC when
amplifier is ON. Setting this bit internally connects
amplifier input to 0v. Hence, corresponding ADC
output can be used in software to eliminate ampli-
fier-offset error.
0: Calibration off
1: Calibration on. (The input voltage of the amp is
set to 0V)
Note:
It is advised to use this bit to calibrate the
ADC when the amplifier is ON. Setting this bit in-
ternally connects the amplifier input to 0v. Hence,
the corresponding ADC output can be used in soft-
ware to eliminate an amplifier-offset error.
Bit 3 =
SLOW
Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
7
0
EOC
SPEED ADON
0
CH3
CH2
CH1
CH0
Channel Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
CH2
0
0
0
0
1
1
1
CH1
0
0
1
1
0
0
1
CH0
0
1
0
1
0
1
0
7
0
D9
D8
D7
D6
D5
D4
D3
D2
7
0
0
0
0
AMP
CAL
SLOW
AMP-
SEL
D1
D0
f
ADC
f
CPU
/2
f
CPU
f
CPU
/4
SLOW SPEED
0
0
1
0
1
x
1
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