參數(shù)資料
型號： ST7FLITE10F1M6
廠商： 意法半導體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI
中文描述： 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，4定時器，微控制器的SPI
文件頁數(shù)： 129/131頁
文件大?。?/td> 2046K
代理商： ST7FLITE10F1M6
ST7LITE1
129/131
17 REVISION HISTORY
Table 27. Revision History
Date
Revision
Description of Changes
July 03
1.3
Changed
section 3 on page 9
and
Figure 3
Added note on RC oscillator in
section 7 on page 23
(main features) and changed
section
7.1 on page 23
: removed reference to ST7LITE10 in RCCR table
Changed
Figure 12 on page 25
(CLKIN/2, OSC/2)
Added note in
section 7.4 on page 26
(external clock source paragraph)
Changed
section 13.3.1 on page 93
: f
CLKIN
instead of f
OSC
Added note in the description of OSC option bit and in
Table 23 on page 122
Revision number incremented from 1.3 to 2.0 due to Internal Document Management Sys-
tem change
Modified Caution to pin n°12 (SO20) or pin n°7 (DIP20) and added caution to PB0 and PB1
in
Table 1 on page 7
Changed Caution in
section 4.4 on page 13
Removed “optional” referring to VDD in
Figure 4 on page 13
In
section 4.5.1 on page 14
: Changed 1st sentence and Clarification of Flash read-out pro-
tection
Replaced CRSR register by SICSR register in
section 7.6.3 on page 32
Added note in
section 7.6.1 on page 29
Reset delay in
section 11.1.3 on page 51
changed to 30μs
MOD00 replaced by 0Ex in
Figure 36 on page 57
Added Note 2 related to Exit from Active Halt,
section 11.2.5 on page 59
Changed “Output Compare Mode” on page 57 and note 1 in
section 11.2.6 on page 60
Replaced FFh by FFFh in the description of OVF bit in
section 11.2.6 on page 60
Removed sentence relating to an effective change only after overflow for CK[1:0],
page 60
Replaced ICAP1 pin by LTIC Pin in
section 11.3.3.3 on page 66
Changed
section 11.4.2 on page 70
Changed
section 11.4.3.3 on page 73
Changed “An interrupt is generated if SPIE = 1 in the SPICSR register” to “An interrupt is
generated if SPIE = 1 in the SPICR register” in description of OVR and MODF bits in
section
11.4.8 on page 78
Added illegal opcode detection to page 1,
section 7.6 on page 29
,
section 12 on page 85
Removed references to “-40°C to +125°C” temperature range in
section 13 on page 91
Altered note 1 for
section 13.2.3 on page 92
removing references to RESET
Changed note 2 in
section 13.2.1 on page 92
Added one row in
section 13.2.2 on page 92
(PB0 and PB1)
Changed
section 13.3 on page 93
f
PLL
value of 1MHz quoted as Typical instead of a Minimum in
section 13.3.4.1 on page 95
In
section 13.4.1 on page 99
: Added note 5 and corrected f
CPU
in SLOW and SLOW WAIT
modes
Added data for Fcpu @ 1MHz into
Section 13.4.1 Supply Current
table.
Updated
Figure 61. Typical IDD in WAIT vs. fCPU
with correct data
Added V
DD
row in
section 13.6.3 on page 102
Changed
section 13.7 on page 103
Added caution to
Figure 65 on page 105
Added V
IL
min value and V
IH
max value in
section 13.8.1 on page 105
and in
section 13.9.1
on page 110
Modified
“Asynchronous RESET Pin” on page 110 (
Figure 82
and
Figure 83
)
Updated f
SCK
in
section 13.10.1 on page 112
to f
CPU
/4 and f
CPU
/2
Updated ADC accuracy table values on
page 115
Changed values in ADC Characteristics table on
page 117
Added note 4 and description relating to Total Percentage in Error and Amplifier Output Off-
set Variation to the ADC Characteristics subsection and table,
page 117
Added note 5 and description relating to Offset Variation in Temperature to ADC Character-
istics subsection and table,
page 117
Dec-2004
2.0
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