參數(shù)資料
型號(hào)： ST7FLITE10F1B6
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI
中文描述： 8位單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，4定時(shí)器，微控制器的SPI
文件頁數(shù)： 62/131頁
文件大?。?/td> 2046K
代理商： ST7FLITE10F1B6
ST7LITE1
62/131
1
12-BIT AUTORELOAD TIMER
(Cont’d)
Bit 4 =
BPEN
Break Pin Enable.
This bit is read/write by software and cleared by
hardware after Reset.
0: Break pin disabled
1: Break pin enabled
Bit 3:0 =
PWM[3:0]
Break Pattern.
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active.
PWMx DUTY CYCLE REGISTER HIGH
(DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
PWMx DUTY CYCLE REGISTER LOW
(DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 =
DCR[11:0]
PWMx Duty Cycle Value
This 12-bit value is written by software. It defin-
esthe duty cycle of the corresponding PWM output
signal (see
Figure 35
).
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see
Figure 35
). In Output
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 =
ICR[11:0]
Input Capture Data
.
This is a 12-bit register which is readable by soft-
ware and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR register when a rising or falling edge
occurs on the ATIC pin. Capture will only be per-
formed when the ICF flag is cleared.
TRANSFER CONTROL REGISTER (TRANCR)
Read/Write
Reset Value: 0000 0001 (01h)
Bits 7:1 Reserved. Forced by hardware to 0.
Bit 0 =
TRAN
Transfer enable
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset.
It allows the value of the DCRx registers to be
transferred to the DCRx shadow registers after the
next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
15
8
0
0
0
0
DCR11 DCR10 DCR9
DCR8
7
0
DCR7
DCR6
DCR5
DCR4
DCR3
DCR2
DCR1
DCR0
15
8
0
0
0
0
ICR11 ICR10
ICR9
ICR8
7
0
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
7
0
0
0
0
0
0
0
0
TRAN
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