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參數(shù)資料
| 型號： | ST7FL05Y0MBTRE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 66/104頁 |
| 文件大?。?/td> | 2151K |
| 代理商： | ST7FL05Y0MBTRE |
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7L05, ST7L09
64/104
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.4.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than or equal
to VDDA (high-level voltage reference) then the
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (VAIN) is lower than or equal to
VSSA (low-level voltage reference) then the con-
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
allotted time.
11.4.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 39:
■ Sample capacitor loading [duration: tSAMPLE]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample
capacitor.
■ A/D conversion [duration: tHOLD]
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum
analog to digital conversion accuracy.
■ The total conversion time:
tCONV = tSAMPLE +tHOLD
While the ADC is on, these two phases are contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behavior is that it min-
imizes the current consumption on the analog pin
in case of single input channel measurement.
11.4.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 11.4.6 for the bit defini-
tions and to Figure 39 for the timings.
ADC Configuration
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the I/O
ports chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
– Select the CH[2:0] bits to assign the analog
channel to be converted.
ADC Conversion
In the CSR register:
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
When a conversion is complete
– The EOC bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the ADCCSR register (with ADON set)
aborts the current conversion, resets the EOC bit
and starts a new conversion.
Figure 39. ADC Conversion Timings
11.4.4 Low Power Modes
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
11.4.5 Interrupts
None
Mode
Description
WAIT
No effect on A/D Converter
HALT
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilization time before ac-
curate conversions can be performed.
ADCCSR WRITE
ADON
EOC BIT SET
tSAMPLE
tHOLD
OPERATION
HOLD
CONTROL
tCONV
1
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| ST7FL09Y0MBE | 制造商:STMicroelectronics 功能描述: |
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