參數(shù)資料
型號(hào)： ST7FL05Y0MATRE
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO16
封裝： 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-16
文件頁(yè)數(shù)： 63/104頁(yè)
文件大?。?/td> 2151K
代理商： ST7FL05Y0MATRE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7L05, ST7L09
61/104
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF =
1, MODF = 1 or OVR = 1 in the SPICSR register
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 15 SPI Master
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 15. SPI Master mode SCK Frequency
70
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Serial Clock
SPR2
SPR1
SPR0
fCPU/4
1
0
fCPU/8
0
fCPU/16
0
1
fCPU/32
1
0
fCPU/64
0
1
0
fCPU/128
0
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST7FL05Y0MB 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with single voltage Flash memory, data EEPROM, ADC, timers, SPI
ST7FL05Y0MBE 制造商:STMicroelectronics 功能描述:
ST7FL05YMAE 制造商:STMicroelectronics 功能描述:MCU 8BIT ST7 CISC 1.5KB FLASH 3.3V/5V 16SOIC - Rail/Tube
ST7FL09Y0MA 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with single voltage Flash memory, data EEPROM, ADC, timers, SPI
ST7FL09Y0MAE 功能描述:8位微控制器 -MCU 8-bit MCU Automotive RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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