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參數(shù)資料
| 型號： | ST78C36A |
| 廠商： | Exar Corporation |
| 英文描述： | ECP/EPP Parallel Printer Port with 16 Byte FIFO(ECP/EPP并行打印機端口（帶16字節(jié)先進(jìn)先出）) |
| 中文描述： | 支持ECP / EPP并行打印機端口（支持ECP / EPP并行打印機端口（帶16字節(jié)先進(jìn)先出），16字節(jié)FIFO） |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 204K |
| 代理商： | ST78C36A |
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ST78C36/36A
6-28
Rev. 4.20
STANDARD DEFINITIONS
Forward direction only.
Compatible Mode, “Centronics” or standard mode.
Reverse direction only.
Nibble mode:
4 bits at a time using status lines for data “Hewlett
Packard Bi-tronics”.
Bi-directional.
EPP:
Enhanced Parallel port-used primarily by non-
printer peripherals.
ECP:
Extended Capability Port-used primarily bt new gen-
eration of printers and scanners.
DATA REGISTER (DATA )
DATA Bit 0-7:
For host output cycles in SPP mode (ECR mode 000)
or PS/2 mode (ECR mode 001), data from the host is
registered at the trailing edge of -IOW. On host input
cycles, data at the peripheral port is passed through to
the host data bus.
ECP FIFO ADDRESS ( ECP-AFIFO )
ECP-AFIFO Bit 0-7:
This port is only available for programmed I/O (non-
DMA), and only has significance for host write. Data
written to this port is stored in the FIFO if FIFO-F = 0
and will be lost if FIFO-F = 1. A 9th FIFO bit (tag) is
set low on write.
A read from this port is the same as a read at 400.
STATUS REGISTER ( DSR )
This status register is read-only except for bit-0, and all
bits are latched for the duration of -IOR.
DSR Bit-0:
If EPP mode is not selected, this bit returns logic one.
During EPP mode, bit-0 will return a high if the EPP 10
msecond TimeOut elapsed during the last EPP read
or write cycle (this TimeOut also aborts the EPP
cycle). This status bit is cleared by exiting EPP mode
or by the host writing a high to bit-0 of this register.
DSR Bit 1-2:
Reserved, logic one.
DSR Bit-3:
The true state of the -ERROR pad.
DSR Bit-4:
The true state of the SLCT pad.
DSR Bit-5:
The true state of the PE(mpty) pad.
DSR Bit-6:
The true state of the -ACK pad.
DSR Bit-7:
The complement of the BUSY pad.
CONTROL REGISTER ( DCR )
DCR Bit-0:
The complement of this bit drives -STROBE, and the
complement of the pad state is returned for read.
DCR Bit-1:
The complement of this bit drives -AUTOFD, and the
complement of the pad state is returned for read.
DCR Bit-2:
This bit drives INIT, and the pad state is returned for
read.
DCR Bit-3:
The complement of this bit drives -SLCTIN, and the
complement of the pad state is returned for read.
DCR Bit-4:
Ack Interrupt Enable set to a high will generate an
interrupt when -ACK is low. When either returns to a
high state, this interrupt source will go in-active. This
interrupt is not pulsed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ST78C36ACJ-0A-EVB | 功能描述:界面開發(fā)工具 Supports 78C36A 44ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| ST78C36ACJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO |
| ST78C36ACJ44-F | 功能描述:接口 - 專用 UART RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| ST78C36ACJ44TR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 16Byte FIFO 5V 44-Pin PLCC T/R 制造商:Exar Corporation 功能描述:ST78C36ACJ44TR-F |
| ST78C36CJ-0A-EVB | 功能描述:界面開發(fā)工具 Supports 78C36 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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